scholarly journals Unity-Gain Zero-Offset CMOS Buffer with Improved Feedforward Path

Electronics ◽  
2021 ◽  
Vol 10 (14) ◽  
pp. 1613
Author(s):  
Waldemar Jendernalik ◽  
Jacek Jakusz ◽  
Robert Piotrowski ◽  
Grzegorz Blakiewicz ◽  
Stanisław Szczepański
Keyword(s):  
Cmos Process ◽  
Rejection Ratio ◽  
Power Supply Rejection Ratio ◽  
Gain Error ◽  
Process Simulations ◽  
Unity Gain ◽  
Input Range ◽  
Similar Area ◽  
Zero Offset ◽  
Cmos Amplifier

A voltage unity-gain zero-offset CMOS amplifier with reduced gain error and increased PSRR (power supply rejection ratio) is proposed. The amplifier uses two feed mechanisms, negative feedback and supporting positive feedforward, to achieve low deviation from unit gain over the entire input range. The circuit, designed in a standard 180-nanometer 1.8-voltage CMOS process, is compared with two known buffers of similar topology, also designed in the same process. Simulations show that, with the same supply (1.8 V), power (1.2 mW), load (12 pF), bandwidth (50 MHz), and similar area (600 µm2), the proposed buffer achieves the lowest gain error (0.3%) and the highest PSRR (72 dB).

Design of CMOS Amplifier Using New CCII Topologies

2011 ◽  
Vol 328-330 ◽  
pp. 1824-1827
Author(s):  
Li Cheng ◽  
Ning Li ◽  
Jia Jian Xi ◽  
Ning Yang
Keyword(s):  
High Performance ◽  
Current Conveyor ◽  
Cmos Process ◽  
Cmos Circuits ◽  
Dynamic Element Matching ◽  
Output Resistance ◽  
Gain Error ◽  
Amplifier Design ◽  
Cmos Amplifier ◽  
Dynamic Element

A high-precision amplifier design in a stander 0.35μm CMOS process was proposed. This design obtains a high-performance by proper application of dynamic element matching to a second generation current conveyor (CCII). In comparison with the traditional CMOS circuits, the proposed approach can not only increase the output swing and decrease output resistance but also compensate the effect of the input offset and 1/fnoise voltage. The simulation results show that the gain error is reduced 38~50 times than the traditional amplifier, and the precision is significantly improved. So the proposed circuit is suitable for the design of special amplifiers used in various detections and signal mediation.

A Novel Low Line Regulation Voltage Reference with No Amplifier

2018 ◽  
Vol 27 (10) ◽  
pp. 1850152 ◽  
Author(s):  
Qiang Li Li ◽  
WanLing Deng ◽  
Xiao Yu Ma ◽  
JunKai Huang
Keyword(s):  
Power Supply ◽  
Output Voltage ◽  
Power Supplies ◽  
Cmos Process ◽  
Voltage Reference ◽  
Bipolar Junction Transistor ◽  
Rejection Ratio ◽  
Power Supply Rejection Ratio ◽  
Junction Transistor ◽  
Simulation Results

A novel low line regulation voltage reference (VR) without an amplifier is presented in this paper. The design is achieved by subtracting two voltages which have the same temperature curves. All circuits use only one Bipolar Junction Transistor (BJT) to decrease the area greatly. Designed with the SMIC 0.18[Formula: see text][Formula: see text]m CMOS process, the simulation results show that the output voltage is 0.902[Formula: see text]V at TT process corner when the power supply is larger than 1.7[Formula: see text]V. The temperature coefficient (TC) is 3.6[Formula: see text]ppm/[Formula: see text]C to 7.4[Formula: see text]ppm/[Formula: see text]C at different power supplies and process corners. The simulated power supply rejection ratio (PSRR) is [Formula: see text]80[Formula: see text]dB at TT process corner when the power supply is 2.5[Formula: see text]V, and the PSRR at different process corners are almost the same. The line regulation of the proposed circuit is 0.005[Formula: see text]mV/V.

scholarly journals A 76db 828nv/√Hz Low Noise Bio Signal OTA For Neural Signal Recording Applications

2018 ◽  
Vol 7 (3.3) ◽  
pp. 48
Author(s):  
Sarin Vijay Mythry ◽  
D Jackuline Moni
Keyword(s):  
Low Frequency ◽  
Low Noise ◽  
Cmos Process ◽  
Gain Bandwidth ◽  
Rejection Ratio ◽  
Power Supply Rejection Ratio ◽  
Research Article ◽  
Different Types ◽  
The Common ◽  
Low Amplitude

The low frequency, low amplitude biomedical signals which created a tremendous demand amongst clinicians and neuroscience researchers are to be amplified in the range of millihertz to kilohertz by rejecting the dc offsets. This research article presents a Bio Signal OTA (Bio-OTA) with 76dB gain, 828nV/ 16Hz"> noise and 390nW power is designed in 90nm CMOS process and also a brief survey on the different types of OTAs used for neuro recording applications is discussed. The Wilson current mirror is used to design 1volt Bio-OTA. The Common mode rejection ratio (CMRR) is obtained as 75dB, power supply rejection ratio (PSRR) is above 88dB and gain bandwidth product (GBW) is 223MHz.  

scholarly journals Design Strategies and Architectures for Ultra-Low-Voltage Delta-Sigma ADCs

Electronics ◽  
2021 ◽  
Vol 10 (10) ◽  
pp. 1156
Author(s):  
Lorenzo Benvenuti ◽  
Alessandro Catania ◽  
Giuseppe Manfredini ◽  
Andrea Ria ◽  
Massimo Piotto ◽  
...  
Keyword(s):  
Low Voltage ◽  
Flicker Noise ◽  
Supply Voltage ◽  
Cmos Process ◽  
Clock Frequency ◽  
Design Environment ◽  
Ultra Low Power ◽  
Analog Cmos ◽  
Gain Error ◽  
Dc Gain

The design of ultra-low voltage analog CMOS integrated circuits requires ad hoc solutions to counteract the severe limitations introduced by the reduced voltage headroom. A popular approach is represented by inverter-based topologies, which however may suffer from reduced finite DC gain, thus limiting the accuracy and the resolutions of pivotal circuits like analog-to-digital converters. In this work, we discuss the effects of finite DC gain on ultra-low voltage ΔΣ modulators, focusing on the converter gain error. We propose an ultra-low voltage, ultra-low power, inverter-based ΔΣ modulator with reduced finite-DC-gain sensitivity. The modulator employs a two-stage, high DC-gain, switched-capacitor integrator that applies a correlated double sampling technique for offset cancellation and flicker noise reduction; it also makes use of an amplifier that implements a novel common-mode stabilization loop. The modulator was designed with the UMC 0.18 μm CMOS process to operate with a supply voltage of 0.3 V. It was validated by means of electrical simulations using the CadenceTM design environment. The achieved SNDR was 73 dB, with a bandwidth of 640 Hz, and a clock frequency of 164 kHz, consuming only 200.5 nW. It achieves a Schreier Figure of Merit of 168.1 dB. The proposed modulator is also able to work with lower supply voltages down to 0.15 V with the same resolution and a lower power consumption despite of a lower bandwidth. These characteristics make this design very appealing in sensor interfaces powered by energy harvesting sources.

Design of High Gain Folded Cascode OTA-Based Transconductance–Capacitance Loop Filter for PLL Applications

2021 ◽  
pp. 2150263
Author(s):  
Priti Gupta ◽  
Sanjay Kumar Jana
Keyword(s):  
Power Consumption ◽  
Supply Voltage ◽  
High Gain ◽  
Cmos Process ◽  
Operational Transconductance Amplifier ◽  
Loop Filter ◽  
Transconductance Amplifier ◽  
Dc Gain ◽  
Unity Gain ◽  
Folded Cascode

This paper deals with the designing of low-power transconductance–capacitance-based loop filter. The folded cascode-based operational transconductance amplifier (OTA) is designed in this paper with the help of quasi-floating bulk MOSFET that achieved the DC gain of 88.61[Formula: see text]dB, unity gain frequency of 97.86[Formula: see text]MHz and power consumption of 430.62[Formula: see text][Formula: see text]W. The proposed OTA is compared with the exiting OTA structure which showed 19.50% increase in DC gain and 15.11% reduction in power consumption. Further, the proposed OTA is used for the designing of transconductance–capacitance-based loop filter that has been operated at [Formula: see text]3[Formula: see text]dB cut-off frequency of 30.12[Formula: see text]MHz with the power consumption of 860.90[Formula: see text][Formula: see text]W at the supply voltage of [Formula: see text][Formula: see text]V. The transistor-level simulation has been done in 0.18[Formula: see text][Formula: see text]m CMOS process.

A 1-mm2 CMOS-pipelined ADC with integrated folded cascode operational amplifier

2020 ◽  
Vol 37 (4) ◽  
pp. 205-213
Author(s):  
Norhamizah Idros ◽  
Zulfiqar Ali Abdul Aziz ◽  
Jagadheswaran Rajendran
Keyword(s):  
Operational Amplifier ◽  
Open Loop ◽  
Cmos Process ◽  
Silicon Area ◽  
Content Type ◽  
Op Amp ◽  
Dc Gain ◽  
Input Range ◽  
Folded Cascode ◽  
The Impact

Purpose The purpose of this paper is to demonstrate the acceptable performance by using the limited input range towards lower open-loop DC gain operational amplifier (op-amp) of an 8-bit pipelined analog-to-digital converter (ADC) for mobile communication application. Design/methodology/approach An op-amp with folded cascode configuration is designed to provide the maximum open-loop DC gain without any gain-boosting technique. The impact of low open-loop DC gain is observed and analysed through the results of pre-, post-layout simulations and measurement of the ADC. The fabrication process technology used is Silterra 0.18-µm CMOS process. The silicon area by the ADC is 1.08 mm2. Findings Measured results show the differential non-linearity (DNL) error, integral non-linearity (INL) error, signal-to-noise ratio (SNR) and spurious-free dynamic range (SFDR) are within −0.2 to +0.2 LSB, −0.55 LSB for 0.4 Vpp input range, 22 and 27 dB, respectively, with 2 MHz input signal at the rate of 64 MS/s. The static power consumption is 40 mW with a supply voltage of 1.8 V. Originality/value The experimental results of ADC showed that by limiting the input range to ±0.2 V, this ADC is able to give a good reasonable performance. Open-loop DC gain of op-amp plays a critical role in ADC performance. Low open-loop DC gain results in stage-gain error of residue amplifier and, thus, leads to nonlinearity of output code. Nevertheless, lowering the input range enhances the linearity to ±0.2 LSB.

scholarly journals A 3GSps 12-bit Four-Channel Time-Interleaved Pipelined ADC in 40 nm CMOS Process

Electronics ◽  
2019 ◽  
Vol 8 (12) ◽  
pp. 1551 ◽  
Author(s):  
Jianwen Li ◽  
Xuan Guo ◽  
Jian Luan ◽  
Danyu Wu ◽  
Lei Zhou ◽  
...  
Keyword(s):  
Dynamic Range ◽  
Cmos Process ◽  
Pipelined Adc ◽  
Least Significant Bit ◽  
Analog To Digital ◽  
Capacitor Mismatch ◽  
Gain Error ◽  
Spurious Free Dynamic Range ◽  
Time Interleaved ◽  
Free Dynamic

This paper presents a four-channel time-interleaved 3GSps 12-bit pipelined analog-to-digital converter (ADC). The combination of master clock sampling and delay-adjusting is adopted to remove the time skew due to channel mismatches. An early comparison scheme is used to minimize the non-overlapping time, where a custom-designed latch is developed to replace the typical non-overlapping clock generator. By using the dither capacitor to generate an equivalent direct current input, a zero-input-based calibration is developed to correct the capacitor mismatch and inter-stage gain error. Fabricated in a 40 nm CMOS process, the ADC achieves a signal-to-noise-and-distortion ratio (SNDR) of 57.8 dB and a spurious free dynamic range (SFDR) of 72 dB with a 23 MHz input tone. It can achieve an SNDR above 52.3 dB and an SFDR above 61.5 dB across the entire first Nyquist zone. The differential and integral nonlinearities are −0.93/+0.73 least significant bit (LSB) and −2.8/+4.3 LSB, respectively. The ADC consumes 450 mW powered at 1.8V, occupies an active area of 3 mm × 1.3 mm. The calculated Walden figure of merit reaches 0.44 pJ/step.

scholarly journals A Comprehensive Comparison of EMI Immunity in CMOS Amplifier Topologies

Electronics ◽  
2019 ◽  
Vol 8 (10) ◽  
pp. 1181 ◽  
Author(s):  
Simone Becchetti ◽  
Anna Richelli ◽  
Luigi Colalongo ◽  
Zsolt Kovacs-Vajna
Keyword(s):  
Electromagnetic Interference ◽  
Printed Circuit Board ◽  
Complementary Metal Oxide Semiconductor ◽  
Circuit Board ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Fair Comparison ◽  
Comprehensive Comparison ◽  
Folded Cascode ◽  
Cmos Amplifier

This paper provides the results of a comprehensive comparison between complementary metal oxide semiconductor (CMOS) amplifiers with low susceptibility to electromagnetic interference (EMI). They represent the state-of-the-art in low EMI susceptibility design. An exhaustive scenario for EMI pollution has been considered: the injected interference can indeed directly reach the amplifier pins or can be coupled from the printed circuit board (PCB) ground. This is also a key point for evaluating the susceptibility from EMI coupled to the output pin. All of the amplifiers are re-designed in a United Microelectronics Corporation (UMC) 180 nm CMOS process in order to have a fair comparison. The topologies investigated and compared are basically derived from the Miller and the folded cascode ones, which are well-known and widely used by CMOS analog designers.

scholarly journals Design a Bioamplifier with High CMRR

VLSI Design ◽  
2013 ◽  
Vol 2013 ◽  
pp. 1-5 ◽  
Author(s):  
Yu-Ming Hsiao ◽  
Miin-Shyue Shiau ◽  
Kuen-Han Li ◽  
Jing-Jhong Hou ◽  
Heng-Shou Hsu ◽  
...  
Keyword(s):  
Biomedical Applications ◽  
Process Variations ◽  
Cmos Technology ◽  
Rejection Ratio ◽  
Self Bias ◽  
High Cmrr ◽  
Three Stages ◽  
Low Offset ◽  
Cmos Amplifier ◽  
Very High

A CMOS amplifier with differential input and output was designed for very high common-mode rejection ratio (CMRR) and low offset. This design was implemented by the 0.35 μm CMOS technology provided by TSMC. With three stages of amplification and by balanced self-bias, a voltage gain of 80 dB with a CMRR of 130 dB was achieved. The related input offset was as low as 0.6 μV. In addition, the bias circuits were designed to be less sensitive to the power supply. It was expected that the whole amplifier was then more independent of process variations. This fact was confirmed in this study by simulation. With the simulation results, it is promising to exhibit an amplifier with high performances for biomedical applications.

A 12-bit 350 MS/s Single-Channel Pipeline ADC with 75 dB SFDR in 0.18 μm BiCMOS

2019 ◽  
Vol 28 (03) ◽  
pp. 1950044
Author(s):  
Jie Sun ◽  
Jianhui Wu
Keyword(s):  
Power Efficiency ◽  
Single Channel ◽  
Pipeline Adc ◽  
Fully Integrated ◽  
Rejection Ratio ◽  
Power Supply Rejection Ratio ◽  
Low Leakage ◽  
Low Leakage Current ◽  
Sige Bicmos ◽  
Supply Rejection

A 12-bit 350[Formula: see text]MS/s ADC with 75[Formula: see text]dB SFDR fabricated in 0.18[Formula: see text][Formula: see text]m SiGe BiCMOS process is presented. To improve the power efficiency, the ADC employs a novel residue amplifier (RA) by exploiting the hetero-junction bipolar transistor (HBT). We also propose a fast comparator to save time for the residue settling of pipeline stages. A fully integrated reference buffer with “negative bootstrap power” (NBP) is proposed to improve both high power supply rejection ratio (PSRR) and ground supply rejection ratio (GSRR). A bandgap reference (BGR) with ultra-low leakage current start-up loop is also presented. The measured results show that with Nyquist input, the SFDR achieves 75[Formula: see text]dB and 63[Formula: see text]dB SNDR up to 350[Formula: see text]MS/s and consumes 180[Formula: see text]mW (only ADC core) with 580[Formula: see text]fj/cov Waldon FOM.

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