Layout Overlay Techniques to Improve Failure Analysis

1998 ◽  
Author(s):  
Christian Burmer ◽  
Siegfried Görlich ◽  
Siegfried Pauthner
Keyword(s):  
Failure Analysis ◽  
Focused Ion Beam ◽  
New Technologies ◽  
Ion Beam ◽  
Image Correlation ◽  
Microelectronic Devices ◽  
Overlay Technique ◽  
Correlation Techniques ◽  
Navigation Software ◽  
Image Format

Abstract New layout overlay technique has been developed based on standard image correlation techniques to support failure analysis in modern microelectronic devices, which are critical to analyze because they are realized in new technologies using sub-ìm design rules, chemical mechanical polishing techniques (CMP) and autorouted design techniques. As the new technique is realized as an extension of a standard CAD-navigation software and as it makes use of standard image format "TIFF" for data input, which is available at all modern equipments for failure analysis, these technique can be applied to all modern failure analysis methods. Here examples are given for three areas of application: circuit modification using Focused Ion Beam (FIB), support of preparation for backside inspection and fault localization using emission microscopy.

Applications of Focused Ion Beam Technology in Bonding Failure Analysis for Microelectronic Devices

2011 ◽  
Vol 58-60 ◽  
pp. 2171-2176 ◽  
Author(s):  
Yuan Chen ◽  
Xiao Wen Zhang
Keyword(s):  
Failure Analysis ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Failure Mechanisms ◽  
Microelectronic Device ◽  
Mechanism Study ◽  
Basic Principles ◽  
The Past ◽  
Microelectronic Devices ◽  
Bonding Failure

Focused ion beam (FIB) system is a powerful microfabrication tool which uses electronic lenses to focus the ion beam even up to nanometer level. The FIB technology has become one of the most necessary failure analysis and failure mechanism study tools for microelectronic device in the past several years. Bonding failure is one of the most common failure mechanisms for microelectronic devices. But because of the invisibility of the bonding interface, it is difficult to analyze this kind of failure. The paper introduced the basic principles of FIB technology. And two cases for microelectronic devices bonding failure were analyzed successfully by FIB technology in this paper.

Direct Plan View FIB Liftout for Near-Surface Defect Analysis in TEM

2013 ◽  
Author(s):  
Max L. Lifson ◽  
Carla M. Chapman ◽  
D. Philip Pokrinchak ◽  
Phyllis J. Campbell ◽  
Greg S. Chrisman ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Silicon Germanium ◽  
Focused Ion Beam ◽  
Surface Defects ◽  
Ion Beam ◽  
Misfit Dislocations ◽  
Tem Analysis ◽  
Plan View ◽  
Near Surface ◽  
Straightforward Method

Abstract Plan view TEM imaging is a powerful technique for failure analysis and semiconductor process characterization. Sample preparation for near-surface defects requires additional care, as the surface of the sample needs to be protected to avoid unintentionally induced damage. This paper demonstrates a straightforward method to create plan view samples in a dual beam focused ion beam (FIB) for TEM studies of near-surface defects, such as misfit dislocations in heteroepitaxial growths. Results show that misfit dislocations are easily imaged in bright-field TEM and STEM for silicon-germanium epitaxial growth. Since FIB tools are ubiquitous in semiconductor failure analysis labs today, the plan view method presented provides a quick to implement, fast, consistent, and straightforward method of generating samples for TEM analysis. While this technique has been optimized for near-surface defects, it can be used with any application requiring plan view TEM analysis.

Fast Turn-around Failure Analysis of Metal Interconnection Using FIB and LA ICP-MS

2010 ◽  
Author(s):  
Zixiao Pan ◽  
Wei Wei ◽  
Fuhe Li
Keyword(s):  
Failure Analysis ◽  
Inductively Coupled Plasma ◽  
Structural Damage ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Detection Sensitivity ◽  
Chemical Contamination ◽  
Inductively Coupled ◽  
Minimal Sample ◽  
Icp Ms

Abstract This paper introduces our effort in failure analysis of a 200 nm thick metal interconnection on a glass substrate and covered with a passivation layer. Structural damage in localized areas of the metal interconnections was observed with the aid of focused ion beam (FIB) cross-sectioning. Laser ablation inductively coupled plasma mass spectroscopy (LA ICP-MS) was then applied to the problematic areas on the interconnection for chemical survey. LA ICP-MS showed direct evidence of localized chemical contamination, which has likely led to corrosion (or over-etching) of the metal interconnection and the assembly failure. Due to the high detection sensitivity of LA ICP-MS and its compatibility with insulating material analysis, minimal sample preparation is required. As a result, the combination of FIB and LA ICP-MS enabled successful meso-scale failure analysis with fast turnaround and reasonable cost.

Logical-to-Physical Device Navigation using Place-and-Route Data as an Alternative to LVS

2006 ◽  
Author(s):  
Roger Nicholson
Keyword(s):  
Failure Analysis ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Traditional Methods ◽  
Navigation Data ◽  
Use Of Time ◽  
Place And Route ◽  
Physical Layout

Abstract Logical-to-physical device navigation for failure analysis is often used to drive physical probers and focused ion beam tools. Traditional methods of creating navigation data rely upon the use of time consuming Layout-versus-Schematic (LVS) based methods. By using existing place-and-route data, full cross-linked navigation between schematic and physical layout may be achieved in a fraction of the time that it takes for the LVS methods to be used. Place-and-route data offers significantly more information to the analyst than LVS based data.

Solving the Voltage Contrast on Floating Substrate with Standard FA Toolset

2016 ◽  
Author(s):  
Julien Goxe ◽  
Béatrice Vanhuffel ◽  
Marie Castignolles ◽  
Thomas Zirilli
Keyword(s):  
Electron Microscope ◽  
Scanning Electron Microscope ◽  
Sample Preparation ◽  
Failure Analysis ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Silicon On Insulator ◽  
Mixed Signal ◽  
Voltage Contrast ◽  
Scanning Electron

Abstract Passive Voltage Contrast (PVC) in a Scanning Electron Microscope (SEM) or a Focused Ion Beam (FIB) is a key Failure Analysis (FA) technique to highlight a leaky gate. The introduction of Silicon On Insulator (SOI) substrate in our recent automotive analog mixed-signal technology highlighted a new challenge: the Bottom Oxide (BOX) layer, by isolating the Silicon Active Area from the bulk made PVC technique less effective in finding leaky MOSFET gates. A solution involving sample preparation performed with standard FA toolset is proposed to enhance PVC on SOI substrate.

High-Throughput, Site-Specific Sample Prep of Ultra-Thin TEM Lamella for Process Metrology and Failure Analysis

2012 ◽  
Author(s):  
Roger Alvis ◽  
Jeff Blackwood ◽  
Sang-Hoon Lee ◽  
Matthew Bray
Keyword(s):  
Sample Preparation ◽  
Failure Analysis ◽  
Process Monitoring ◽  
High Throughput ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Memory Devices ◽  
Site Specific ◽  
Critical Dimensions ◽  
Tem Lamella

Abstract Semiconductor devices with critical dimensions less than 20nm are now being manufactured in volume. A challenge facing the failure analysis and process-monitoring community is two-fold. The first challenge of TEM sample prep of such small devices is that the basic need to end-point on a feature-of-interest pushes the imaging limit of the instrument being used to prepare the lamella. The second challenge posed by advanced devices is to prepare an artifact-free lamella from non-planar devices such as finFETs as well as from structures incorporating ‘non-traditional’ materials. These challenges are presently overcome in many advanced logic and memory devices in the focused ion beam-based TEM sample preparation processes by inverting the specimen prior to thinning to electron transparency. This paper reports a highthroughput method for the routine preparation of artifact-free TEM lamella of 20nm thickness, or less.

Failure Modes, Reliability Analysis and Case Studies on the Integration of Copper and Low-K Technology

2004 ◽  
Author(s):  
Huixian Wu ◽  
James Cargo ◽  
Huixian Wu ◽  
Marvin White
Keyword(s):  
Failure Analysis ◽  
Case Studies ◽  
Cross Section ◽  
Focused Ion Beam ◽  
Failure Modes ◽  
Ion Beam ◽  
Copper Interconnects ◽  
Wet Chemical ◽  
Low K ◽  
Section Analysis

Abstract The integration of copper interconnects and low-K dielectrics will present novel failure modes and reliability issues to failure analysts. This paper discusses failure modes related to Cu/low-K technology. Here, physical failure analysis (FA) techniques including deprocessing and cross-section analysis have been developed. The deprocessing techniques include wet chemical etching, reactive ion etching, chemical mechanical polishing and a combination of these techniques. Case studies on different failure modes related to Cu/low k technology are discussed: copper voiding, copper extrusion; electromigration stress failure; dielectric cracks; delamination-interface adhesion; and FA on circuit-under-pad. For the cross-section analysis of copper/low-K samples, focused ion beam techniques have been developed. Scanning electron microscopy, EDX, and TEM analytical analysis have been used for failure analysis for Cu/low-K technology. Various failure modes and reliability issues have also been addressed.

Localization Techniques on a 0.15um CMOS Device: Charge Pump Failure Analysis

2002 ◽  
Author(s):  
Hui Pan ◽  
Thomas Gibson
Keyword(s):  
Failure Analysis ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Electrical Characterization ◽  
Charge Pump ◽  
Front Side ◽  
Pump Failure ◽  
Electrical Failure ◽  
Optical Proximity Correction ◽  
A Charge

Abstract In recent years, there have been many advances in the equipment and techniques used to isolate faults. There are many options available to the failure analyst. The available techniques fall into the categories of electrical, photonic, thermal and electron/ion beam [1]. Each technique has its advantages and its limitations. In this paper, we introduce a case of successful failure analysis using a combination of several fault localization techniques on a 0.15um CMOS device with seven layers of metal. It includes electrical failure mode characterization, front side photoemission, backside photoemission, Focused Ion Beam (FIB), Scanning Electron Microscope (SEM) and liquid crystal. Electrical characterization along with backside photoemission proved most useful in this case as a poly short problem was found to be causing a charge pump failure. A specific type of layout, often referred to as a hammerhead layout, and the use of Optical Proximity Correction (OPC) contributed to the poly level shorts.

Failure Analysis Strategies for Multistacked Memory Devices with TSV Interconnects

2015 ◽  
Author(s):  
Frank Altmann ◽  
Christian Grosse ◽  
Falk Naumann ◽  
Jens Beyersdorfer ◽  
Tony Veches
Keyword(s):  
Failure Analysis ◽  
Focused Ion Beam ◽  
Failure Modes ◽  
Ion Beam ◽  
Memory Devices ◽  
Metallographic Cross Section ◽  
Electron Beam Induced Current ◽  
Thermal Simulations ◽  
Lock In ◽  
Non Destructive

Abstract In this paper we will demonstrate new approaches for failure analysis of memory devices with multiple stacked dies and TSV interconnects. Therefore, TSV specific failure modes are studied on daisy chain test samples. Two analysis flows for defect localization implementing Electron Beam Induced Current (EBAC) imaging and Lock-in-Thermography (LIT) as well as adapted Focused Ion Beam (FIB) preparation and defect characterization by electron microscopy will be discussed. The most challenging failure mode is an electrical short at the TSV sidewall isolation with sub-micrometer dimensions. It is shown that the leakage path to a certain TSV within the stack can firstly be located by applying LIT to a metallographic cross section and secondly pinpointing by FIB/SEM cross-sectioning. In order to evaluate the potential of non-destructive determination of the lateral defect position, as well as the defect depth from only one LIT measurement, 2D thermal simulations of TSV stacks with artificial leakages are performed calculating the phase shift values per die level.

Molding of Three-Dimensional Microcomponents

2006 ◽  
Author(s):  
W. N. P. Hung ◽  
M. M. Agnihotri ◽  
M. Y. Ali ◽  
S. Yuan
Keyword(s):  
Focused Ion Beam ◽  
New Technologies ◽  
Electrical Discharge Machining ◽  
Ion Beam ◽  
Semiconductor Industry ◽  
Three Dimensional ◽  
Cost Effective ◽  
Molecular Structures ◽  
Minimum Size ◽  
Ion Beam Sputtering

Traditional micromanufacturing has been developed for semiconductor industry. Selected micro electrical mechanical systems (MEMS) have been successfully developed and implemented in industry. Since current MEMS are designed for manufacture using microelectronics processes, they are limited to two-dimensional profiles and semiconductor based materials. Such shape and material constraints would exclude many applications that require biocompatibility, dynamic stress, and high ductility. New technologies are sought to fabricate three dimensional microcomponents using robust materials for demanding applications. To be cost effective, such microdevices must be economically mass producible. Molding is one of the promising replication techniques to mass produce components from polymers and polymer-based composites. This paper presents the development of a micromolding process to produce thermoplastic microcomponents. Mold design required precision fitting and was integrated with a vacuum pump to minimize air trap in mold cavities. Nickel and aluminum mold inserts were used for the study; their cavities were fabricated by combinations of available micromachining processes like laser micromachining, micromilling, micro electrical discharge machining, and focused ion beam sputtering. High and low density polyethylene, polystyrene polymers were used for this study. The effects of polymer molecular structures, molding temperature, time, and pressure on molding results were studied. Simulation of stress in the microcomponents, plastic flow in microchannels, and mold defects was performed and compare with experimental data. The research results showed that a microcomponent can be fabricated to the minimum size of 10 ± 1μm (0.0004 inch) with surface roughness <10 nm Rt. Molding of micro-size geartrains and orthopedic meso-size fasteners was completed to illustrate the capability of this process.

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