Fast EM Immortality Analysis for Multi-Segment Copper Interconnect Wires

2019 ◽  
pp. 67-96
Author(s):  
Sheldon Tan ◽  
Mehdi Tahoori ◽  
Taeyoung Kim ◽  
Shengcheng Wang ◽  
Zeyu Sun ◽  
...  
Keyword(s):  
Copper Interconnect

Experimental Characterization of the Reliability of 3-Terminal Dual-Damascene Copper Interconnect Trees

2002 ◽  
Vol 716 ◽  
Author(s):  
C. L. Gan ◽  
C. V. Thompson ◽  
K. L. Pey ◽  
W. K. Choi ◽  
F. Wei ◽  
...  
Keyword(s):  
Stress Conditions ◽  
Experimental Characterization ◽  
Contact Lines ◽  
Tree Structures ◽  
Similar Test ◽  
Dual Damascene ◽  
Copper Interconnect ◽  
Test Conditions

AbstractElectromigration experiments have been carried out on simple Cu dual-damascene interconnect tree structures consisting of straight via-to-via (or contact-to-contact) lines with an extra via in the middle of the line. As with Al-based interconnects, the reliability of a segment in this tree strongly depends on the stress conditions of the connected segment. Beyond this, there are important differences in the results obtained under similar test conditions for Al-based and Cu-based interconnect trees. These differences are thought to be associated with variations in the architectural schemes of the two metallizations. The absence of a conducting electromigrationresistant overlayer in Cu technology, and the possibility of liner rupture at stressed vias lead to significant differences in tree reliabilities in Cu compared to Al.

Sample Preparation and Preservation for TEM Analysis of Copper Interconnect Integrated Circuit

2004 ◽  
Author(s):  
Qiang Gao ◽  
Mark Zhang ◽  
Ming Li ◽  
Chorng Niou ◽  
W.T. Kary Chien
Keyword(s):  
Integrated Circuit ◽  
Thermal Exposure ◽  
Ambient Atmosphere ◽  
Ion Milling ◽  
Tem Analysis ◽  
Single Beam ◽  
Copper Interconnect ◽  
Beam Modulation ◽  
Area Of Interest ◽  
Transmission Electron

Abstract This paper examines copper-interconnect integrated circuit transmission electron microscope (TEM) sample contamination. It investigates the deterioration of the sample during ion milling and storage and introduces prevention techniques. The paper discusses copper grain agglomeration issues barrier/seed step coverage checking. The high temperature needed for epoxy solidifying was found to be harmful to sidewall coverage checking of seed. Single beam modulation using a glass dummy can efficiently prevent contamination of the area of interest in a TEM sample during ion milling. Adoption of special low-temperature cure epoxy resin can greatly reduce thermal exposure of the sample and prevent severe agglomeration of copper seed on via sidewall. TEM samples containing copper will deteriorate when stored in ordinary driers and sulphur contamination was found at the deteriorated point on the sample. Isolation of the sample from the ambient atmosphere has been verified to be very effective in protecting the TEM sample from deterioration.

An investigation of copper interconnect deposition bath ageing by electrochemical impedance spectroscopy

2007 ◽  
Vol 38 (4) ◽  
pp. 457-468 ◽  
Author(s):  
C. Gabrielli ◽  
P. Moçotéguy ◽  
H. Perrot ◽  
D. Nieto-Sanz ◽  
A. Zdunek
Keyword(s):  
Electrochemical Impedance Spectroscopy ◽  
Impedance Spectroscopy ◽  
Electrochemical Impedance ◽  
Copper Interconnect

Microstructural characterization of inlaid copper interconnect lines

2001 ◽  
Vol 30 (4) ◽  
pp. 320-330 ◽  
Author(s):  
Paul R. Besser ◽  
Ehrenfried Zschech ◽  
Werner Blum ◽  
Delrose Winter ◽  
Richard Ortega ◽  
...  
Keyword(s):  
Microstructural Characterization ◽  
Copper Interconnect ◽  
Interconnect Lines

Fabrication and Thermo-Mechanical Characterization of Fine Pitch All-Copper Interconnect

2012 ◽  
Vol 159 (9) ◽  
pp. D532-D537 ◽  
Author(s):  
Rajarshi Saha ◽  
Hyo-Chol Koo ◽  
Ping Nicole An ◽  
Paul A. Kohl
Keyword(s):  
Mechanical Characterization ◽  
Copper Interconnect ◽  
Fine Pitch

The Stepwise Cross-sectional Crystalline Analysis of the Stress Induced Voiding in Cu Interconnect

2006 ◽  
Vol 914 ◽  
Author(s):  
Hyo-Jong Lee ◽  
Heung Nam Han ◽  
Suk Hoon Kang ◽  
Jeong-Yun Sun ◽  
Kyu Hwan Oh
Keyword(s):  
Grain Boundary ◽  
Twin Boundary ◽  
Triple Junction ◽  
Hydrostatic Stress ◽  
Electron Backscattered Diffraction ◽  
Cross Sectional ◽  
Copper Interconnect ◽  
Crystallographic Study ◽  
Cu Interconnect ◽  
Planar Electron

AbstractIn a crystallographic study of stress induced voiding of copper interconnect, the planar electron backscattered diffraction analysis showed that the void was initiated at the triple junction of the grain boundaries, not at the junction of the twin boundary and grain boundary. By using stepwise cross-sectional crystalline investigation for the void, it was possible to rebuild 3D crystalline structure near the void. From the stress calculation based on the measured crystalline structures, the hydrostatic stress was highly concentrated at the triple junction of the twin boundary and grain boundary, but experimentally, there was no voiding at that. The voiding in the copper interconnect may depend mainly on the boundary instability.

Effect of mass transport along interfaces and grain boundaries on copper interconnect degradation

2004 ◽  
Vol 812 ◽  
Author(s):  
Ehrenfried Zschech ◽  
Moritz A. Meyer ◽  
Eckhard Langer
Keyword(s):  
Mass Transport ◽  
Grain Boundaries ◽  
Void Formation ◽  
Degradation Process ◽  
Copper Interconnects ◽  
Second Phase ◽  
Copper Interconnect ◽  
Void Evolution ◽  
Two Phases

AbstractIn-situ SEM electromigration studies were performed at fully embedded via/line interconnect structures to visualize the time-dependent void evolution in inlaid copper interconnects. Void formation, growth and movement, and consequently interconnect degradation, depend on both interface bonding and copper microstructure. Two phases are distinguished for the electromigration-induced interconnect degradation process: In the first phase, agglomerations of vacancies and voids are formed at interfaces and grain boundaries, and voids move along weak interfaces. In the second phase of the degradation process, they merge into a larger void which subsequently grows into the via and eventually causes the interconnect failure. Void movement along the copper line and void growth in the via are discontinuous processes, whereas their step-like behavior is caused by the copper microstructure. Directed mass transport along inner surfaces depends strongly on the crystallographic orientation of the copper grains. Electromigration lifetime can be drastically increased by changing the copper/capping layer interface. Both an additional CoWP coating and a local copper alloying with aluminum increase the bonding strength of the top interface of the copper interconnect line, and consequently, electromigration-induced mass transport and degradation processes are reduced significantly.

Bundled SWCNT for Global VLSI Interconnects

2020 ◽  
pp. 160-188
Author(s):  
Raj Kumar ◽  
Shashi Bala
Keyword(s):  
Mechanical Properties ◽  
Carbon Nanotube ◽  
Transition Time ◽  
Equivalent Model ◽  
Suitable Material ◽  
Vlsi Interconnects ◽  
Copper Interconnect ◽  
Parallel Lines ◽  
Bus Architecture ◽  
Interconnect Material

Carbon nanotube (CNT) has been declared the most attractive and suitable material for VLSI sub-micron technology. Because of CNT's phenomenal physical, electrical, and mechanical properties, it is more advantageous than copper interconnect material. In this chapter, RLC equivalent model of bundled single-wall CNT (SWCNT) is presented by using driver-interconnect-load (DIL) system with CMOS driver. The crosstalk delay is calculated for two-line bus architecture made of two parallel lines (i.e., upper as aggressor and lower as victim). From the simulation, it has been observed that crosstalk delay increases with increase in interconnect length and transition time, whereas it decreases with increased spacing between the lines (aggressor and victim). However, crosstalk delay decreases as the number of tubes in a bundle increases.

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