High Speed, Low Matchline Voltage Swing and Search Line Activity TCAM Cell Array Design in 14 nm FinFET Technology

2019 ◽  
pp. 465-473
Author(s):  
K. Prasanth ◽  
M. Ramireddy ◽  
T. Keerthi priya ◽  
S. Ravindrakumar
Keyword(s):  
High Speed ◽  
Cell Array ◽  
Array Design ◽  
Voltage Swing ◽  
Search Line

Simulation and Analysis of different CMOS Full Adders for Delay Optimisation

2021 ◽  
Vol 9 (9) ◽  
pp. 66-70
Author(s):  
Nakul C. Kubsad
Keyword(s):  
Power Dissipation ◽  
High Speed ◽  
Digital Signal ◽  
Full Adder ◽  
Digital Signal Processors ◽  
Transmission Gate ◽  
Logical Operations ◽  
Recent Advancement ◽  
Voltage Swing ◽  
Signal Processors

Abstract: Full adder circuit is one among the fundamental and necessary digital part. The full adder is be a part of microprocessors, digital signal processors etc. It's needed for the arithmetic and logical operations. Full adder design enhancements are necessary for recent advancement. The requirement of an adder cell is to provide high speed, consume low power and provide high voltage swing. This paper analyses and compares 3 adders with completely different logic designs (Conventional, transmission gate & pseudo NMOS) for transistor count, power dissipation and delay. The simulation is performed in Cadence virtuoso tool with accessible GPDK – 180nm kit. Transmission gate full adder has sheer advantage of high speed, fewer space and also it shows higher performance in terms of delay. Keywords: Delay, power dissipation, voltage, transistor sizing.

Cross-Layer Dual Modular Redundancy Hardened Scheme of Flip-Flop Design Based on Sense-Amplifier

2020 ◽  
pp. 2120003
Author(s):  
Zhengfeng Huang ◽  
Zian Su ◽  
Tianming Ni ◽  
Qi Xu ◽  
Haochen Qi ◽  
...  
Keyword(s):  
Power Consumption ◽  
High Speed ◽  
Fault Tolerant ◽  
Cross Layer ◽  
Charge Sharing ◽  
Single Node ◽  
Flip Flop ◽  
Sense Amplifier ◽  
Modular Redundancy ◽  
Voltage Swing

As the demand for low-power and high-speed logic circuits increases, the design of differential flip-flops based on sense-amplifier (SAFF), which have excellent power and speed characteristics, has become more and more popular. Conventional SAFF (Con SAFF) and improved SAFF designs focus more on the improvement of speed and power consumption, but ignore their Single-Event-Upset (SEU) sensitivity. In fact, SAFF is more susceptible to particle impacts due to the small voltage swing required for differential input in the master stage. Based on the SEU vulnerability of SAFF, this paper proposes a novel scheme, namely cross-layer Dual Modular Redundancy (DMR), to improve the robustness of SAFF. That is, unit-level DMR technology is performed in the master stage, while transistor-level stacking technology is used in the slave stage. This scheme can be applied to some current typical SAFF designs, such as Con SAFF, Strollo SAFF, Ahmadi SAFF, Jeong SAFF, etc. Detailed HSPICE simulation results demonstrate that hardened SAFF designs can not only fully tolerate the Single Node Upset of sensitive nodes, but also partially tolerate the Double Node Upset caused by charge sharing. Besides, compared with the conventional DMR hardened scheme, the proposed cross-layer DMR hardened scheme not only has the same fault-tolerant characteristics, but also greatly reduces the delay, area and power consumption.

A RAIL-TO-RAIL BUFFER AMPLIFIER FOR LCD DRIVER

2011 ◽  
Vol 20 (07) ◽  
pp. 1377-1387 ◽  
Author(s):  
CHIH-WEN LU ◽  
CHING-MIN HSIAO
Keyword(s):  
High Speed ◽  
Liquid Crystal Display ◽  
Stable State ◽  
Cmos Technology ◽  
Offset Voltage ◽  
Rail To Rail ◽  
Lcd Driver ◽  
Display Driver ◽  
Buffer Amplifier ◽  
Voltage Swing

A high-speed low-power rail-to-rail buffer amplifier, which is suitable for liquid crystal display driver applications, is proposed. An offset voltage is intentionally built in the second stage to cut off the transistors of last stage from the output node in the stable state and hence achieve low dc power consumption. The input referred offset voltage due to the built-in offset is very small. The buffer draws little current while static but has a large driving capability while transient. An experimental prototype buffer amplifier implemented in a 0.35-μm CMOS technology demonstrates that the circuit can operate under a wide power supply range. Quiescent current of 5 μA is measured. The buffer exhibits the settling time of 1.5 μs for a voltage swing of 0.1 ~ (VDD – 0.1) V under a 600 pF capacitance load. The area of this buffer is 30 × 98 μm2. The measured data show that the proposed output buffer amplifier is very suitable for LCD driver applications.

A Novel Cell-Array Design for Single Chamber SOFC Microstack

Fuel Cells ◽  
2009 ◽  
Vol 9 (5) ◽  
pp. 717-721 ◽  
Author(s):  
Mingliang Liu ◽  
Zhe Lü ◽  
Bo Wei ◽  
Xiqiang Huang ◽  
Kongfa Chen ◽  
...  
Keyword(s):  
Cell Array ◽  
Array Design ◽  
Single Chamber

scholarly journals A 10 Gbps 4-PAM CMOS serial link transmitter with pre-emphasis

2021 ◽  
Author(s):  
Minghai Li
Keyword(s):  
Electromagnetic Interference ◽  
High Speed ◽  
Characteristic Impedance ◽  
Current Mode ◽  
Serial Link ◽  
Chip Area ◽  
Power Efficient ◽  
Fully Differential ◽  
Active Inductors ◽  
Voltage Swing

This thesis presents the design of 10 Gbps 4-PAM CMOS serial link transmitters. A new area-power efficient fully differential CMOS current-mode serial link transmitter with a proposed 2/4-PAM signaling configuration and a new pre-emphasis scheme is presented. The pre-emphasis inthe analog domain and the use of de-emphasis approach decres pre-emphasis power and chip area. The high-speed operation of the transmitter is achieved from the small voltage swing of critical nodes of the transmitter, shunt peaking with active inductors, multiplexing-at-input approach, the distributed multiplexing nodes, and the low characteristic impedance of the channels. The fully differential and bidirectional current-mode signaling minimizes the noise injected to the power and ground rails and the electromagnetic interference exerted from the channels to neighboring devices. A PLL containing a proposed five-stage VCO is implemented to generate multi-phase on -chip clocks. The proposed VCO minimized the phase noise by keeping a constant rising and falling time. Simulation results demonstrate that the current received at the far end of a 10 cm FR-4 microstriop has a 4-PAM current eye width of 185 ps and eye hight of 1.21 mA. It consumes 57.6 mW power with differnetial delay block, or 19.2 mW power with inverter buffer chain. The total transistor area of the transmitter is 26.845 ....excluding the delay block.

Using Silvar-Lisco for Logic Cell Array Design

1989 ◽  
Vol 26 (1-2) ◽  
pp. 92-99 ◽  
Author(s):  
Martin Bolton ◽  
David Milford
Keyword(s):  
Student Motivation ◽  
Cell Array ◽  
Array Design ◽  
Gate Arrays

Instead of gate arrays, the logic cell array (LCA) has been used as the implementation medium in an undergraduate design exercise. Software has been written to link the SL-2000 database to the LCA layout and routing system (XACT). The result has been improved student motivation and a higher proportion of completed designs.

scholarly journals Design and Characterization of the Next Generation Nanowire Amplifiers

VLSI Design ◽  
2008 ◽  
Vol 2008 ◽  
pp. 1-5
Author(s):  
Sotoudeh Hamedi-Hagh ◽  
Ahmet Bindal
Keyword(s):  
High Speed ◽  
Field Effect Transistors ◽  
Channel Length ◽  
Next Generation ◽  
Short Channel ◽  
Surrounding Gate ◽  
Channel Effects ◽  
Gate Control ◽  
Voltage Swing

Vertical nanowire surrounding gate field effect transistors (SGFETs) provide full gate control over the channel to eliminate short-channel effects. This paper presents design and characterization of a differential pair amplifier using NMOS and PMOS SGFETs with a 10 nm channel length and a 2 nm channel radius. The amplifier dissipates 5 μW power and provides 5 THz bandwidth with a voltage gain of 16, a linear output voltage swing of 0.5 V, and a distortion better than 3% from a 1.8 V power supply and a 20 aF capacitive load. The 2nd- and 3rd-order harmonic distortions of the amplifier are −40 dBm and −52 dBm, respectively, and the 3rd-order intermodulation is −24 dBm for a two-tone input signal with 10 mV amplitude and 10 GHz frequency spacing. All these parameters indicate that vertical nanowire surrounding gate transistors are promising candidates for the next generation high-speed analog and VLSI technologies.

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