An energy-efficient high-speed CMOS hybrid comparator with reduced delay time in 40-nm CMOS process

In nanoscale regime as the CMOS process technology continues to scale, the standard copper (Cu) interconnect will become a major hurdle for onchip communication due to high resistivity and electromigration. This paper presents the comprehensive evaluation of mixed CNT bundle interconnects and investigates their prospects as a low power high-speed interconnect for future nanoscale-integrated circuits. The performance of mixed CNT bundle interconnect is examined with carbon nanotube field effect transistor (CNFET) as a driver and compared with the traditional interconnect, that is, CMOS driver on Cu interconnect. All HSPICE simulations are carried out at operating frequency of 1 GHz and it is found that mixed CNT bundle interconnects with CNFET as the driver can potentially provide a substantial delay reduction over traditional interconnects implemented at 32 nm process technology. Similarly, the CNFET driver with mixed CNT bundle as interconnect is more energy efficient than the traditional interconnect at all supply voltages (VDD) from 0.9 V to 0.3 V.

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Design and Analysis of an Energy-Efficient High-Speed CMOS Double-Tail Dynamic Comparator with Reduced Kickback Noise Effect

Journal of Circuits System and Computers ◽

10.1142/s0218126619501573 ◽

2019 ◽

Vol 28 (09) ◽

pp. 1950157 ◽

Cited By ~ 3

Author(s):

Avaneesh K. Dubey ◽

R. K. Nagaria

Keyword(s):

Energy Efficient ◽

High Speed ◽

Input Voltage ◽

Mean Value ◽

Cmos Process ◽

Total Delay ◽

Dynamic Comparator ◽

Amplifier Stage ◽

The Mean ◽

Design Style

This paper presents a novel high-speed and highly energy-efficient double-tail dynamic comparator. In order to achieve high speed, a hybrid design style is adopted for pre-amplifier stage and a new design is proposed for latch stage, which enhances the speed and reduces the effect of kickback noise. The latch stage delay and energy efficiency of the proposed design are optimized with respect to the width of each transistor. To verify the outcomes, the proposed comparator is simulated using 45[Formula: see text]nm and 180[Formula: see text]nm CMOS process. Monte Carlo simulation is also done for each parameter. The 45[Formula: see text]nm result shows that the comparator has the total delay as low as 104.3[Formula: see text]ps and consumes only 0.288[Formula: see text]fJ of energy per conversion from a 0.8[Formula: see text]V supply. The mean value of input voltage error due to kickback noise is found as 306[Formula: see text]nV.

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Research on Prediction of High-Speed Rail Trains Delay Time

CICTP 2020 ◽

10.1061/9780784482933.184 ◽

2020 ◽

Author(s):

Jing Shi ◽

Qiyuan Peng ◽

Ling Liu

Keyword(s):

Delay Time ◽

High Speed ◽

High Speed Rail

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Neuro-Inspired Computing with Spin-VCSELs

Applied Sciences ◽

10.3390/app11094232 ◽

2021 ◽

Vol 11 (9) ◽

pp. 4232

Author(s):

Krishan Harkhoe ◽

Guy Verschaffelt ◽

Guy Van der Sande

Keyword(s):

Processing Speed ◽

Delay Time ◽

High Speed ◽

State Of The Art ◽

Polarization Modulation ◽

Time Interval ◽

Computing Technique ◽

High Modulation ◽

Short Time ◽

Modulation Speed

Delay-based reservoir computing (RC), a neuromorphic computing technique, has gathered lots of interest, as it promises compact and high-speed RC implementations. To further boost the computing speeds, we introduce and study an RC setup based on spin-VCSELs, thereby exploiting the high polarization modulation speed inherent to these lasers. Based on numerical simulations, we benchmarked this setup against state-of-the-art delay-based RC systems and its parameter space was analyzed for optimal performance. The high modulation speed enabled us to have more virtual nodes in a shorter time interval. However, we found that at these short time scales, the delay time and feedback rate heavily influence the nonlinear dynamics. Therefore, and contrary to other laser-based RC systems, the delay time has to be optimized in order to obtain good RC performances. We achieved state-of-the-art performances on a benchmark timeseries prediction task. This spin-VCSEL-based RC system shows a ten-fold improvement in processing speed, which can further be enhanced in a straightforward way by increasing the birefringence of the VCSEL chip.

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A High-Speed Temperature Sensor with Low Supply Sensitivity for SoC Thermal Monitoring

Journal of Circuits System and Computers ◽

10.1142/s0218126618501165 ◽

2018 ◽

Vol 27 (07) ◽

pp. 1850116

Author(s):

Yuanxin Bao ◽

Wenyuan Li

Keyword(s):

Temperature Sensor ◽

Conversion Rate ◽

High Speed ◽

Supply Voltage ◽

Ring Oscillator ◽

Temperature Sensitive ◽

Cmos Process ◽

Digital Code ◽

Thermal Monitoring ◽

Worst Case

A high-speed low-supply-sensitivity temperature sensor is presented for thermal monitoring of system on a chip (SoC). The proposed sensor transforms the temperature to complementary to absolute temperature (CTAT) frequency and then into digital code. A CTAT voltage reference supplies a temperature-sensitive ring oscillator, which enhances temperature sensitivity and conversion rate. To reduce the supply sensitivity, an operational amplifier with a unity gain for power supply is proposed. A frequency-to-digital converter with piecewise linear fitting is used to convert the frequency into the digital code corresponding to temperature and correct nonlinearity. These additional characteristics are distinct from the conventional oscillator-based temperature sensors. The sensor is fabricated in a 180[Formula: see text]nm CMOS process and occupies a small area of 0.048[Formula: see text]mm2 excluding bondpads. After a one-point calibration, the sensor achieves an inaccuracy of [Formula: see text][Formula: see text]1.5[Formula: see text]C from [Formula: see text]45[Formula: see text]C to 85[Formula: see text]C under a supply voltage of 1.4–2.4[Formula: see text]V showing a worst-case supply sensitivity of 0.5[Formula: see text]C/V. The sensor maintains a high conversion rate of 45[Formula: see text]KS/s with a fine resolution of 0.25[Formula: see text]C/LSB, which is suitable for SoC thermal monitoring. Under a supply voltage of 1.8[Formula: see text]V, the maximum energy consumption per conversion is only 7.8[Formula: see text]nJ at [Formula: see text]45[Formula: see text]C.

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A 1.55-to-32-Gb/s Four-Lane Transmitter with 3-Tap Feed Forward Equalizer and Shared PLL in 28-nm CMOS

Electronics ◽

10.3390/electronics10161873 ◽

2021 ◽

Vol 10 (16) ◽

pp. 1873

Author(s):

Chen Cai ◽

Xuqiang Zheng ◽

Yong Chen ◽

Danyu Wu ◽

Jian Luan ◽

...

Keyword(s):

Data Transmission ◽

High Speed ◽

Data Rate ◽

Quality Data ◽

Cmos Process ◽

Voltage Controlled Oscillator ◽

Feed Forward ◽

Fully Integrated ◽

Output Driver ◽

28 Nm

This paper presents a fully integrated physical layer (PHY) transmitter (TX) suiting for multiple industrial protocols and compatible with different protocol versions. Targeting a wide operating range, the LC-based phase-locked loop (PLL) with a dual voltage-controlled oscillator (VCO) was integrated to provide the low jitter clock. Each lane with a configurable serialization scheme was adapted to adjust the data rate flexibly. To achieve high-speed data transmission, several bandwidth-extended techniques were introduced, and an optimized output driver with a 3-tap feed-forward equalizer (FFE) was proposed to accomplish high-quality data transmission and equalization. The TX prototype was fabricated in a 28-nm CMOS process, and a single-lane TX only occupied an active area of 0.048 mm2. The shared PLL and clock distribution circuits occupied an area of 0.54 mm2. The proposed PLL can support a tuning range that covers 6.2 to 16 GHz. Each lane's data rate ranged from 1.55 to 32 Gb/s, and the energy efficiency is 1.89 pJ/bit/lane at a 32-Gb/s data rate and can tune an equalization up to 10 dB.

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Dual-shot dynamics and ultimate frequency of all-optical magnetic recording on GdFeCo

Light Science & Applications ◽

10.1038/s41377-020-00451-z ◽

2021 ◽

Vol 10 (1) ◽

Author(s):

Sicong Wang ◽

Chen Wei ◽

Yuanhua Feng ◽

Hongkun Cao ◽

Wenzhe Li ◽

...

Keyword(s):

Magnetization Reversal ◽

Energy Efficient ◽

High Speed ◽

Data Transfer ◽

Laser Pulses ◽

Time Resolved ◽

All Optical ◽

Fs Laser ◽

High Speed Data ◽

Natural Way

AbstractAlthough photonics presents the fastest and most energy-efficient method of data transfer, magnetism still offers the cheapest and most natural way to store data. The ultrafast and energy-efficient optical control of magnetism is presently a missing technological link that prevents us from reaching the next evolution in information processing. The discovery of all-optical magnetization reversal in GdFeCo with the help of 100 fs laser pulses has further aroused intense interest in this compelling problem. Although the applicability of this approach to high-speed data processing depends vitally on the maximum repetition rate of the switching, the latter remains virtually unknown. Here we experimentally unveil the ultimate frequency of repetitive all-optical magnetization reversal through time-resolved studies of the dual-shot magnetization dynamics in Gd27Fe63.87Co9.13. Varying the intensities of the shots and the shot-to-shot separation, we reveal the conditions for ultrafast writing and the fastest possible restoration of magnetic bits. It is shown that although magnetic writing launched by the first shot is completed after 100 ps, a reliable rewriting of the bit by the second shot requires separating the shots by at least 300 ps. Using two shots partially overlapping in space and minimally separated by 300 ps, we demonstrate an approach for GHz magnetic writing that can be scaled down to sizes below the diffraction limit.

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A Low-Power 12-Bit 20 MS/s Asynchronously Controlled SAR ADC for WAVE ITS Sensor Based Applications

Sensors ◽

10.3390/s21072260 ◽

2021 ◽

Vol 21 (7) ◽

pp. 2260

Author(s):

Khuram Shehzad ◽

Deeksha Verma ◽

Danial Khan ◽

Qurat Ul Ain ◽

Muhammad Basim ◽

...

Keyword(s):

Power Consumption ◽

Low Power ◽

High Speed ◽

Intelligent Transportation System ◽

Cmos Process ◽

Process Technology ◽

Back Issue ◽

Digital To Analog Converter ◽

Analog To Digital ◽

Switching Method

A low power 12-bit, 20 MS/s asynchronously controlled successive approximation register (SAR) analog-to-digital converter (ADC) to be used in wireless access for vehicular environment (WAVE) intelligent transportation system (ITS) sensor based application is presented in this paper. To optimize the architecture with respect to power consumption and performance, several techniques are proposed. A switching method which employs the common mode charge recovery (CMCR) switching process is presented for capacitive digital-to-analog converter (CDAC) part to lower the switching energy. The switching technique proposed in our work consumes 56.3% less energy in comparison with conventional CMCR switching method. For high speed operation with low power consumption and to overcome the kick back issue in the comparator part, a mutated dynamic-latch comparator with cascode is implemented. In addition, to optimize the flexibility relating to the performance of logic part, an asynchronous topology is employed. The structure is fabricated in 65 nm CMOS process technology with an active area of 0.14 mm2. With a sampling frequency of 20 MS/s, the proposed architecture attains signal-to-noise distortion ratio (SNDR) of 65.44 dB at Nyquist frequency while consuming only 472.2 µW with 1 V power supply.

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NanoLEDs for energy-efficient and gigahertz-speed spike-based sub-λ neuromorphic nanophotonic computing

Nanophotonics ◽

10.1515/nanoph-2020-0177 ◽

2020 ◽

Vol 9 (13) ◽

pp. 4149-4162 ◽

Cited By ~ 2

Author(s):

Bruno Romeira ◽

José M. L. Figueiredo ◽

Julien Javaloyes

Keyword(s):

Neural Networks ◽

Energy Efficient ◽

High Speed ◽

Dynamic Properties ◽

Optical Computing ◽

Differential Conductance ◽

Rate Equations ◽

Dynamical Equations ◽

Electrical Modulation ◽

High Bandwidth

AbstractEvent-activated biological-inspired subwavelength (sub-λ) photonic neural networks are of key importance for future energy-efficient and high-bandwidth artificial intelligence systems. However, a miniaturized light-emitting nanosource for spike-based operation of interest for neuromorphic optical computing is still lacking. In this work, we propose and theoretically analyze a novel nanoscale nanophotonic neuron circuit. It is formed by a quantum resonant tunneling (QRT) nanostructure monolithic integrated into a sub-λ metal-cavity nanolight-emitting diode (nanoLED). The resulting optical nanosource displays a negative differential conductance which controls the all-or-nothing optical spiking response of the nanoLED. Here we demonstrate efficient activation of the spiking response via high-speed nonlinear electrical modulation of the nanoLED. A model that combines the dynamical equations of the circuit which considers the nonlinear voltage-controlled current characteristic, and rate equations that takes into account the Purcell enhancement of the spontaneous emission, is used to provide a theoretical framework to investigate the optical spiking dynamic properties of the neuromorphic nanoLED. We show inhibitory- and excitatory-like optical spikes at multi-gigahertz speeds can be achieved upon receiving exceptionally low (sub-10 mV) synaptic-like electrical activation signals, lower than biological voltages of 100 mV, and with remarkably low energy consumption, in the range of 10–100 fJ per emitted spike. Importantly, the energy per spike is roughly constant and almost independent of the incoming modulating frequency signal, which is markedly different from conventional current modulation schemes. This method of spike generation in neuromorphic nanoLED devices paves the way for sub-λ incoherent neural elements for fast and efficient asynchronous neural computation in photonic spiking neural networks.

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LOW-POWER, PARALLEL INTERFACE WITH CONTINUOUS-TIME ADAPTIVE PASSIVE EQUALIZER AND CROSSTALK CANCELLATION

International Journal of High Speed Electronics and Systems ◽

10.1142/s0129156405003260 ◽

2005 ◽

Vol 15 (02) ◽

pp. 459-476

Author(s):

C. PATRICK YUE ◽

JAEJIN PARK ◽

RUIFENG SUN ◽

L. RICK CARLEY ◽

FRANK O'MAHONY

Keyword(s):

Low Power ◽

Electromagnetic Interference ◽

Continuous Time ◽

High Speed ◽

High Performance ◽

Process Variations ◽

Cmos Process ◽

Power Circuit ◽

Crosstalk Cancellation ◽

Circuit Components

This paper presents the low-power circuit techniques suitable for high-speed digital parallel interfaces each operating at over 10 Gbps. One potential application for such high-performance I/Os is the interface between the channel IC and the magnetic read head in future compact hard disk systems. First, a crosstalk cancellation technique using a novel data encoding scheme is introduced to suppress electromagnetic interference (EMI) generated by the adjacent parallel I/Os . This technique is implemented utilizing a novel 8-4-PAM signaling with a data look-ahead algorithm. The key circuit components in the high-speed interface transceiver including the receive sampler, the phase interpolator, and the transmitter output driver are described in detail. Designed in a 0.13-μm digital CMOS process, the transceiver consumes 310 mW per 10-Gps channel from a I-V supply based on simulation results. Next, a 20-Gbps continuous-time adaptive passive equalizer utilizing on-chip lumped RLC components is described. Passive equalizers offer the advantages of higher bandwidth and lower power consumption compared with conventional designs using active filter. A low-power, continuous-time servo loop is designed to automatically adjust the equalizer frequency response for the optimal gain compensation. The equalizer not only adapts to different channel characteristics, but also accommodates temperature and process variations. Implemented in a 0.25-μm, 1P6M BiCMOS process, the equalizer can compensate up to 20 dB of loss at 10 GHz while only consumes 32 mW from a 2.5-V supply.

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