Design and Analysis of an Energy-Efficient High-Speed CMOS Double-Tail Dynamic Comparator with Reduced Kickback Noise Effect

2019 ◽  
Vol 28 (09) ◽  
pp. 1950157 ◽  
Author(s):  
Avaneesh K. Dubey ◽  
R. K. Nagaria
Keyword(s):  
Energy Efficient ◽  
High Speed ◽  
Input Voltage ◽  
Mean Value ◽  
Cmos Process ◽  
Total Delay ◽  
Dynamic Comparator ◽  
Amplifier Stage ◽  
The Mean ◽  
Design Style

This paper presents a novel high-speed and highly energy-efficient double-tail dynamic comparator. In order to achieve high speed, a hybrid design style is adopted for pre-amplifier stage and a new design is proposed for latch stage, which enhances the speed and reduces the effect of kickback noise. The latch stage delay and energy efficiency of the proposed design are optimized with respect to the width of each transistor. To verify the outcomes, the proposed comparator is simulated using 45[Formula: see text]nm and 180[Formula: see text]nm CMOS process. Monte Carlo simulation is also done for each parameter. The 45[Formula: see text]nm result shows that the comparator has the total delay as low as 104.3[Formula: see text]ps and consumes only 0.288[Formula: see text]fJ of energy per conversion from a 0.8[Formula: see text]V supply. The mean value of input voltage error due to kickback noise is found as 306[Formula: see text]nV.

Influence of Curve Sharpness on Torsional Loading of the Tibia in Running

2002 ◽  
Vol 18 (3) ◽  
pp. 218-230 ◽  
Author(s):  
Ryuji Kawamoto ◽  
Yusuke Ishige ◽  
Koji Watarai ◽  
Senshi Fukashiro
Keyword(s):  
High Speed ◽  
Mean Value ◽  
Rigid Bodies ◽  
Rate Of Change ◽  
Quasi Equilibrium ◽  
Running Injuries ◽  
Curved Track ◽  
The Mean ◽  
Free Body ◽  
As Stress

The purpose of this study was to test quantitatively the hypothesis that, as runners run along a more sharply curved track, greater torsional moments act on their tibiae. Six male participants were asked to run along a straight track and along counterclockwise curved tracks with turn radii of 15 m (gentle) and 5 m (sharp) at 3.5 m s–1. Data were collected using two high-speed cameras and force platforms. Each participant’s left (corresponding to the inside of the curves) foot and tibia were modeled as a system of coupled rigid bodies. For analysis, net axial moments acting on both ends of the tibia were calculated using free-body analysis. The torsional moment acting on the tibia was determined from the quasi-equilibrium balance of the tibial axial moments based on the assumption that the rate of change of the angular momentum about the tibial axis was negligible. The results showed that the torsional moments, which were in the direction of external rotational loading of the proximal tibiae, increased as the track curvature became sharper. Furthermore, the mean value of the maximum torsional moments, while running on a sharply curved track (28.5 Nm), was significantly higher than the values obtained while running on a straight track (11.0 Nm, p < .01) and on a gently curved track (12.2 Nm, p < .01). In conclusion, the present study has quantitatively confirmed that as runners run along a more sharply curved track, greater torsional moments act on their tibiae. The findings imply that athletes prone to tibial running injuries such as stress fractures should avoid repetitive running on sharply curved paths.

scholarly journals A 12-bit 30 MS/s Successive Approximation-Register Analog-to-Digital Converter with Foreground Digital Calibration Algorithm

Symmetry ◽  
2020 ◽  
Vol 12 (1) ◽  
pp. 165
Author(s):  
Shouping Li ◽  
Yang Guo ◽  
Jianjun Chen ◽  
Bin Liang
Keyword(s):  
Successive Approximation ◽  
High Speed ◽  
Low Noise ◽  
Digital Calibration ◽  
Cmos Process ◽  
Analog To Digital Converter ◽  
Digital Converter ◽  
Dynamic Comparator ◽  
Analog To Digital ◽  
Calibration Algorithm

This paper presents a foreground digital calibration algorithm based on a dynamic comparator that aims to reduce comparator offset and capacitor mismatch, as well as improve the performance of the successive approximation analog-to-digital converter (SARADC). The dynamic comparator is designed with two preamplifiers and one latch to facilitate high speed, high precision, and low noise. The foreground digital calibration algorithm provides high speed with minimal area consumption. This design is implemented on a 12-bit 30 MS/s SARADC with a standard 0.13 μm Complementary Metal Oxide Semiconductor (CMOS) process. The simulation Nyquist 68.56 dB signal-to-noise-and-distortion ratio (SNDR) and 84.45 dBc spurious free dynamic range (SFDR) at 30 MS/s, differential nonlinearity (DNL) and integral nonlinearity (INL) are within 0.64 Least Significant Bits (LSB) and 1.3 LSB, respectively. The ADC achieves an effective number of bits (ENOB) of 11.08 and a figure-of-merit (FoM) of 39.45 fJ/conv.-step.

scholarly journals Derivation of Motor Mean Phase Currents in PMSM Drives Operating with Low Switching-to-Fundamental Frequency Ratio

2019 ◽  
Vol 4 (1) ◽  
pp. 95-102
Author(s):  
Leszek Jarzebowicz
Keyword(s):  
Fundamental Frequency ◽  
Frequency Ratio ◽  
High Speed ◽  
Pulse Width Modulation ◽  
Permanent Magnet Synchronous Motor ◽  
Sampling Technique ◽  
Mean Value ◽  
High Rate ◽  
Linear Current ◽  
The Mean

AbstractPulse width modulation (PWM) of inverter output voltage causes the waveforms of motor phase currents to consist of distinctive ripples. In order to provide suitable feedback for the motor current controllers, the mean value must be extracted from the currents’ waveforms in every PWM cycle. A common solution to derive the mean phase currents is to sample their value at the midpoint of a symmetrical PWM cycle. Using an assumption of linear current changes in steady PWM subintervals, this midpoint sample corresponds to the mean current in the PWM cycle. This way no hardware filtering or high-rate current sampling is required. Nevertheless, the assumption of linear current changes has been recently reported as over simplistic in permanent magnet synchronous motor (PMSM) drives operating with low switching-to-fundamental frequency ratio (SFFR). This, in turn, causes substantial errors in the representation of the mean phase currents by the midpoint sample. This paper proposes a solution for deriving mean phase currents in low SFFR PMSM drives, which does not rely on the linear current change assumption. The method is based on sampling the currents at the start point of a PWM cycle and correcting the sampled value using a model-based formula that reproduces the current waveforms. Effectiveness of the method is verified by simulation for an exemplary setup of high-speed PMSM drive. The results show that the proposed method decreases the error of determining the mean phase currents approximately 10 times when compared to the classical midpoint sampling technique.

NOISE-AWARE SPLIT-PATH DOMINO LOGIC AND ITS CLOCK DELAYING SCHEME

2007 ◽  
Vol 16 (01) ◽  
pp. 139-154 ◽  
Author(s):  
DONGKYU PARK ◽  
SEOKSOO YOON ◽  
INHWA JUNG ◽  
CHULWOO KIM
Keyword(s):  
High Speed ◽  
Performance Enhancement ◽  
Circuit Simulation ◽  
Logic Circuits ◽  
Logic Circuit ◽  
Cmos Process ◽  
Total Delay ◽  
Domino Logic ◽  
Delay Cell ◽  
Improved Performance

This paper describes an improved domino logic using split-path (SP) and revised clock-delaying (CD) scheme. SP domino logic is a high-speed operation because it ameliorates the charge-sharing problem by splitting the stacked NMOS transistors used for logic evaluation. Additionally, SP domino logic removes the use of signal ordering. Dual threshold voltage (Vt) assignment methodology for the SP domino logic circuit is also proposed in order to provide the improved performance with low power-consumption overhead. Our experimental results of SP domino logic circuit show that the proposed logic provides the performance improvement up to 15% compared to the conventional domino logic circuit, under the same noise conditions. For further performance enhancement of the domino logic, CD methodology is applied. Moreover, an optimized delay cell is proposed to reduce the clock-delay overhead required to compensate the process, voltage, and temperature (PVT) variations. 32-b Han–Carlson prefix adders using the proposed CD SP domino logic circuits and the conventional CD domino logic circuits were designed to verify the performance enhancement of the proposed circuit. Simulation results show that the total delay of the 32-b adder using the proposed circuit is 454 ps of 5.47FO4 in a 0.18-μm CMOS process.

scholarly journals Low Power Continuous-Time Delta-Sigma Modulators Using the Three Stage OTA and Dynamic Comparator

2018 ◽  
Vol 7 (2.16) ◽  
pp. 38
Author(s):  
Anshu Gupta ◽  
Lalita Gupta ◽  
R K. Baghel
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Continuous Time ◽  
High Speed ◽  
Second Order ◽  
Cmos Process ◽  
Sigma Delta Modulator ◽  
Dynamic Comparator ◽  
Sigma Delta ◽  
Delta Sigma

A second-order sigma delta modulator that uses an operational transconductance amplifier as integrator and latch comparator as quantizer. The proposed technique where a low power high gain OTA is used as integrator and another circuit called dynamic latch comparator with two tail transistors and two controlling switches are used to achieve high speed, low power and high resolution in second order delta sigma modulator. It enhances the power efficiency and compactness of the modulator by implementing these blocks as sub modules. A second order modulator has been designed to justify the effectiveness of the proposed design. Technology 180nm CMOS process is used to implement complete second order continuous time sigma delta modulator.  We introduce the sub threshold three stage OTA, which is a way of achieving low distortion operation with input referred noise at 1 KHz is equal to the 2.2647pV/   and with low power consumption of 296.72nW.  A high-speed, low-voltage and a low-power Double-Tail dynamic comparator is also proposed. The proposed structure is contrasted with past dynamic comparators. In this paper, the comparator’s delay will be investigated and systematic analysis are inferred. a novel comparator using two tail transistor is proposed, here circuitry of a customized comparator having two tail is changed for low power dissipation and also it operates fast at little supply voltages. By maintaining the outline and by including couple of transistors, during the regeneration strengthening of positive feedback can be maintained, this results in amazingly diminished delay parameter. It is investigated that in proposed design structure of comparator using two tail transistors, power consumption is reduced and delay time is also diminished to a great extent. The proposed comparator is having maximum clock frequency that is possibly expanded up to 1GHz at voltages of 1 V whereas it is dissipating 10.99 µW of power, individually. By using sub threshold three stage OTA and dynamic standard two tail latch comparator, designed second order sigma delta ADC will consume 29.95µW of power.

scholarly journals Analysis of CNT Bundle and Its Comparison with Copper Interconnect for CMOS and CNFET Drivers

2009 ◽  
Vol 2009 ◽  
pp. 1-6 ◽  
Author(s):  
Abdul Kadir Kureshi ◽  
Mohd. Hasan
Keyword(s):  
Integrated Circuits ◽  
Energy Efficient ◽  
High Speed ◽  
Comprehensive Evaluation ◽  
High Resistivity ◽  
Cmos Process ◽  
Process Technology ◽  
Delay Reduction ◽  
Effect Transistor ◽  
Cu Interconnect

In nanoscale regime as the CMOS process technology continues to scale, the standard copper (Cu) interconnect will become a major hurdle for onchip communication due to high resistivity and electromigration. This paper presents the comprehensive evaluation of mixed CNT bundle interconnects and investigates their prospects as a low power high-speed interconnect for future nanoscale-integrated circuits. The performance of mixed CNT bundle interconnect is examined with carbon nanotube field effect transistor (CNFET) as a driver and compared with the traditional interconnect, that is, CMOS driver on Cu interconnect. All HSPICE simulations are carried out at operating frequency of 1 GHz and it is found that mixed CNT bundle interconnects with CNFET as the driver can potentially provide a substantial delay reduction over traditional interconnects implemented at 32 nm process technology. Similarly, the CNFET driver with mixed CNT bundle as interconnect is more energy efficient than the traditional interconnect at all supply voltages (VDD) from 0.9 V to 0.3 V.

scholarly journals On the Boundary between Nonlinear Jump Phenomenon and Linear Response of Hypoid Gear Dynamics

2011 ◽  
Vol 2011 ◽  
pp. 1-13
Author(s):  
Jun Wang ◽  
Teik C. Lim
Keyword(s):  
Linear Response ◽  
High Speed ◽  
Mean Value ◽  
Dynamic Mesh ◽  
Jump Discontinuity ◽  
Hypoid Gear ◽  
Jump Phenomenon ◽  
The Mean ◽  
Primary Focus ◽  
Point Line

A nonlinear time-varying (NLTV) dynamic model of a hypoid gear pair system with time-dependent mesh point, line-of-action vector, mesh stiffness, mesh damping, and backlash nonlinearity is formulated to analyze the transitional phase between nonlinear jump phenomenon and linear response. It is found that the classical jump discontinuity will occur if the dynamic mesh force exceeds the mean value of tooth mesh force. On the other hand, the propensity for the gear response to jump disappears when the dynamic mesh force is lower than the mean mesh force. Furthermore, the dynamic analysis is able to distinguish the specific tooth impact types from analyzing the behaviors of the dynamic mesh force. The proposed theory is general and also applicable to high-speed spur, helical and spiral bevel gears even though those types of gears are not the primary focus of this paper.

scholarly journals A Low Input Referred Noise Dynamic Comparator for High Speed Applications

2019 ◽  
Vol 8 (4) ◽  
pp. 4768-4772
Keyword(s):  
High Speed ◽  
Cmos Technology ◽  
Pivotal Role ◽  
Clock Frequency ◽  
Output Stage ◽  
Dynamic Comparator ◽  
Mixed Signal ◽  
Low Input ◽  
Mixed Signal Circuits ◽  
Amplifier Stage

Comparators play a pivotal role in design of analog and mixed signal circuits. Comparators employ regenerative feedback both in input pre-amplifier stage and output stage. The designed comparator resolves 5mV with resolution of 8 bits and dissipates 11mW of power using 1.2V supply in 130nm CMOS technology while operating at clock frequency of 1.25 GHz

scholarly journals Calculation of Semiconductor Power Losses of a Three-Phase Quasi-Z-Source Inverter

Electronics ◽  
2020 ◽  
Vol 9 (10) ◽  
pp. 1642
Author(s):  
Ivan Grgić ◽  
Dinko Vukadinović ◽  
Mateo Bašić ◽  
Matija Bubalo
Keyword(s):  
Duty Cycle ◽  
Pulse Width Modulation ◽  
Semiconductor Device ◽  
Operation Mode ◽  
Input Voltage ◽  
Mean Value ◽  
Phase Current ◽  
Switching Losses ◽  
Three Phase ◽  
The Mean

This paper presents two novel algorithms for the calculation of semiconductor losses of a three-phase quasi-Z-source inverter (qZSI). The conduction and switching losses are calculated based on the output current-voltage characteristics and switching characteristics, respectively, which are provided by the semiconductor device manufacturer. The considered inverter has been operated in a stand-alone operation mode, whereby the sinusoidal pulse width modulation (SPWM) with injected 3rd harmonic has been implemented. The proposed algorithms calculate the losses of the insulated gate bipolar transistors (IGBTs) and the free-wheeling diodes in the inverter bridge, as well as the losses of the impedance network diode. The first considered algorithm requires the mean value of the inverter input voltage, the mean value of the impedance network inductor current, the peak value of the phase current, the modulation index, the duty cycle, and the phase angle between the fundamental output phase current and voltage. Its implementation is feasible only for the Z-source-related topologies with the SPWM. The second considered algorithm requires the instantaneous values of the inverter input voltage, the impedance network diode current, the impedance network inductor current, the phase current, and the duty cycle. However, it does not impose any limitations regarding the inverter topology or switching modulation strategy. The semiconductor losses calculated by the proposed algorithms were compared with the experimentally determined losses. Based on the comparison, the correction factor for the IGBT switching energies was determined so the errors of both the algorithms were reduced to less than 12%.

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