High Performance GCM Architecture for the Security of High Speed Network

2017 ◽  
Vol 46 (5) ◽  
pp. 904-922 ◽  
Author(s):  
Vanitha Mohanraj ◽  
R. Sakthivel ◽  
Anand Paul ◽  
Seungmin Rho
Keyword(s):  
High Speed ◽  
High Performance ◽  
High Speed Network

scholarly journals Impact of Modern Virtualization Methods on Timing Precision and Performance of High-Speed Applications

2019 ◽  
Vol 11 (8) ◽  
pp. 179 ◽  
Author(s):  
Veronika Kirova ◽  
Kirill Karpov ◽  
Eduard Siemens ◽  
Irina Zander ◽  
Oksana Vasylenko ◽  
...  
Keyword(s):  
Virtual Environments ◽  
Virtual Environment ◽  
High Speed ◽  
High Performance ◽  
Estimation Accuracy ◽  
Network Applications ◽  
High Speed Network ◽  
Timing Precision ◽  
And Performance ◽  
The Impact

The presented work is a result of extended research and analysis on timing methods precision, their efficiency in different virtual environments and the impact of timing precision on the performance of high-speed networks applications. We investigated how timer hardware is shared among heavily CPU- and I/O-bound tasks on a virtualized OS as well as on bare OS. By replacing the invoked timing methods within a well-known application for estimation of available path bandwidth, we provide the analysis of their impact on estimation accuracy. We show that timer overhead and precision are crucial for high-performance network applications, and low-precision timing methods usage, e.g., the delays and overheads issued by virtualization result in the degradation of the virtual environment. Furthermore, in this paper, we provide confirmation that, by using the methods we intentionally developed for both precise timing operations and AvB estimation, it is possible to overcome the inefficiency of standard time-related operations and overhead that comes with the virtualization. The impacts of negative virtualization factors were investigated in five different environments to define the most optimal virtual environment for high-speed network applications.

PACKET INDEXING PROCESS OPTIMIZED FOR HIGH-SPEED NETWORK PROCESSORS

2005 ◽  
Vol 14 (04) ◽  
pp. 841-860 ◽  
Author(s):  
C. CHAROPOULOS ◽  
F. ANDRITSOPOULOS ◽  
Y. MITSOS ◽  
G. DOUMENIS ◽  
G. STASINOPOULOS
Keyword(s):  
High Speed ◽  
High Performance ◽  
Packet Classification ◽  
Network Processors ◽  
High Speed Network ◽  
Packet Data ◽  
Content Addressable Memories ◽  
Open Addressing ◽  
Discrete Flow ◽  
Significant Size

Most network processors perform some kind of classification on the received packet stream, according to criteria set by the implemented networking application. Packet indexing is an integral part of the packet classification process. Indexing is considered as one of the most processor intensive part of network processing and is often supported by special hardware units. High performance Network processors usually rely upon Content Addressable Memories (CAMs) for the indexing of millions of packets per second into discrete "flow Identifiers" in ATM and IP networks. Most often, the indexing process examines packet data (tags) of significant size, necessitating the use of large CAM devices. This paper proposes an alternative method for searching lengthy tags, using RAM as storage medium instead of the expensive and complex CAMs. The technique applies the open-addressing hashing methodology to provide high speed lookups, close to CAM's performance. Our approach handles efficiently the limitations imposed by the hashing algorithms by appropriately selecting system parameters and resolving hashing collisions. The advantages of the proposed method are evaluated in detail.

scholarly journals High-speed network traffic capturing and processing tools

2021 ◽  
Vol 33 (4) ◽  
pp. 49-68
Author(s):  
Dmitry Victorovich Larin ◽  
Aleksandr Igorevich Getman
Keyword(s):  
Operating Systems ◽  
Network Traffic ◽  
High Speed ◽  
High Performance ◽  
Virtual Network ◽  
Packet Processing ◽  
Commodity Hardware ◽  
High Speed Network ◽  
Traffic Rate ◽  
Network Functions

Network stacks currently implemented in operating systems can no longer cope with the packet rates offered by 10 Gbit Ethernet. Thus, frameworks were developed claiming to offer a faster alternative for this demand. These frameworks enable arbitrary packet processing systems to be built from commodity hardware handling a traffic rate of several 10 Gbit interfaces, entering a domain previously only available to custom-built hardware. In this paper, we survey various frameworks for high-performance packet IO and their interaction with a modular frameworks and specialized virtual network functions software for high-speed packet processing. We introduce a model to estimate and assess the performance of these packet processing frameworks. Moreover, we analyze the performance of the most prominent frameworks based on representative measurements in packet capturing scenarios. Therefore, we provide a comparison between them and select the area of applicability.

Vacuum System to Minimize the Specimen Contamination of High-Performance EM

1977 ◽  
Vol 35 ◽  
pp. 68-69
Author(s):  
N. Yoshimura ◽  
K. Shirota ◽  
T. Etoh
Keyword(s):  
Electron Microscope ◽  
High Speed ◽  
High Performance ◽  
High Vacuum ◽  
Vacuum System ◽  
Pump System ◽  
Pumping System ◽  
Diffusion Pump ◽  
Almost All ◽  
Cascade Type

One of the most important requirements for a high-performance EM, especially an analytical EM using a fine beam probe, is to prevent specimen contamination by providing a clean high vacuum in the vicinity of the specimen. However, in almost all commercial EMs, the pressure in the vicinity of the specimen under observation is usually more than ten times higher than the pressure measured at the punping line. The EM column inevitably requires the use of greased Viton O-rings for fine movement, and specimens and films need to be exchanged frequently and several attachments may also be exchanged. For these reasons, a high speed pumping system, as well as a clean vacuum system, is now required. A newly developed electron microscope, the JEM-100CX features clean high vacuum in the vicinity of the specimen, realized by the use of a CASCADE type diffusion pump system which has been essentially improved over its predeces- sorD employed on the JEM-100C.

PHAX-SCAN: Functional integration of a Scanning Electron Microscope and an energy-dispersive x-ray analyser

1989 ◽  
Vol 47 ◽  
pp. 56-57
Author(s):  
Marc H. Peeters ◽  
Max T. Otten
Keyword(s):  
Electron Microscope ◽  
Scanning Electron Microscope ◽  
High Speed ◽  
High Performance ◽  
Functional Integration ◽  
Energy Dispersive ◽  
X Rays ◽  
X Ray ◽  
High Speed Analysis ◽  
Scanning Electron

Over the past decades, the combination of energy-dispersive analysis of X-rays and scanning electron microscopy has proved to be a powerful tool for fast and reliable elemental characterization of a large variety of specimens. The technique has evolved rapidly from a purely qualitative characterization method to a reliable quantitative way of analysis. In the last 5 years, an increasing need for automation is observed, whereby energy-dispersive analysers control the beam and stage movement of the scanning electron microscope in order to collect digital X-ray images and perform unattended point analysis over multiple locations.The Philips High-speed Analysis of X-rays system (PHAX-Scan) makes use of the high performance dual-processor structure of the EDAX PV9900 analyser and the databus structure of the Philips series 500 scanning electron microscope to provide a highly automated, user-friendly and extremely fast microanalysis system. The software that runs on the hardware described above was specifically designed to provide the ultimate attainable speed on the system.

The bright future of digital imaging in scanning electron microscopy

1993 ◽  
Vol 51 ◽  
pp. 768-769
Author(s):  
M. T. Postek ◽  
A. E. Vladar
Keyword(s):  
Electron Microscopy ◽  
Scanning Electron Microscopy ◽  
Digital Imaging ◽  
High Speed ◽  
High Performance ◽  
Mass Storage ◽  
Analog To Digital ◽  
Central Processing ◽  
Digital Imaging Technology ◽  
Scanning Electron

One of the major advancements applied to scanning electron microscopy (SEM) during the past 10 years has been the development and application of digital imaging technology. Advancements in technology, notably the availability of less expensive, high-density memory chips and the development of high speed analog-to-digital converters, mass storage and high performance central processing units have fostered this revolution. Today, most modern SEM instruments have digital electronics as a standard feature. These instruments, generally have 8 bit or 256 gray levels with, at least, 512 × 512 pixel density operating at TV rate. In addition, current slow-scan commercial frame-grabber cards, directly applicable to the SEM, can have upwards of 12-14 bit lateral resolution permitting image acquisition at 4096 × 4096 resolution or greater. The two major categories of SEM systems to which digital technology have been applied are:In the analog SEM system the scan generator is normally operated in an analog manner and the image is displayed in an analog or "slow scan" mode.

Performance Analysis of Various Multipliers Using 8T-full Adder with 180nm Technology

2020 ◽  
Vol 13 (6) ◽  
pp. 864-870
Author(s):  
Sai Venkatramana Prasada G.S ◽  
G. Seshikala ◽  
S. Niranjana
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
High Speed ◽  
High Performance ◽  
Full Adder ◽  
Fundamental Operation ◽  
Wallace Tree ◽  
Power Delay Product ◽  
The Comparative Study ◽  
Wallace Tree Multiplier

Background: This paper presents the comparative study of power dissipation, delay and power delay product (PDP) of different full adders and multiplier designs. Methods: Full adder is the fundamental operation for any processors, DSP architectures and VLSI systems. Here ten different full adder structures were analyzed for their best performance using a Mentor Graphics tool with 180nm technology. Results: From the analysis result high performance full adder is extracted for further higher level designs. 8T full adder exhibits high speed, low power delay and low power delay product and hence it is considered to construct four different multiplier designs, such as Array multiplier, Baugh Wooley multiplier, Braun multiplier and Wallace Tree multiplier. These different structures of multipliers were designed using 8T full adder and simulated using Mentor Graphics tool in a constant W/L aspect ratio. Conclusion: From the analysis, it is concluded that Wallace Tree multiplier is the high speed multiplier but dissipates comparatively high power. Baugh Wooley multiplier dissipates less power but exhibits more time delay and low PDP.

scholarly journals Ultracompact and low-power-consumption silicon thermo-optic switch for high-speed data

Nanophotonics ◽  
2020 ◽  
Vol 10 (2) ◽  
pp. 937-945
Author(s):  
Ruihuan Zhang ◽  
Yu He ◽  
Yong Zhang ◽  
Shaohua An ◽  
Qingming Zhu ◽  
...  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
High Performance ◽  
Pulse Amplitude ◽  
Telecommunication Networks ◽  
Low Power Consumption ◽  
Power Efficient ◽  
High Speed Data ◽  
On Chip

AbstractUltracompact and low-power-consumption optical switches are desired for high-performance telecommunication networks and data centers. Here, we demonstrate an on-chip power-efficient 2 × 2 thermo-optic switch unit by using a suspended photonic crystal nanobeam structure. A submilliwatt switching power of 0.15 mW is obtained with a tuning efficiency of 7.71 nm/mW in a compact footprint of 60 μm × 16 μm. The bandwidth of the switch is properly designed for a four-level pulse amplitude modulation signal with a 124 Gb/s raw data rate. To the best of our knowledge, the proposed switch is the most power-efficient resonator-based thermo-optic switch unit with the highest tuning efficiency and data ever reported.

Sign in / Sign up

Export Citation Format

Share Document