Optimization of zero-level interlayer dielectric materials for gate-all-around silicon nanowire channel fabrication in a replacement metal gate process

2021 ◽  
Vol 121 ◽  
pp. 105434
Author(s):  
Qingzhu Zhang ◽  
Hailing Tu ◽  
Zhaohao Zhang ◽  
Junjie Li ◽  
Feng Wei ◽  
...  
Keyword(s):  
Silicon Nanowire ◽  
Dielectric Materials ◽  
Metal Gate ◽  
Interlayer Dielectric ◽  
Zero Level

Intrinsic low dielectric behaviour of a highly thermally stable Sr-based metal–organic framework for interlayer dielectric materials

2014 ◽  
Vol 2 (19) ◽  
pp. 3762-3768 ◽  
Author(s):  
Muhammad Usman ◽  
Cheng-Hua Lee ◽  
Dung-Shing Hung ◽  
Shang-Fan Lee ◽  
Chih-Chieh Wang ◽  
...  
Keyword(s):  
Dielectric Constant ◽  
Metal Organic Framework ◽  
Dielectric Materials ◽  
Low Dielectric Constant ◽  
Water Molecules ◽  
Compound A ◽  
Interlayer Dielectric ◽  
Low Dielectric ◽  
Metal Organic ◽  
Organic Framework

A Sr-based metal–organic framework exhibits an intrinsic low dielectric constant after removing the water molecules. A low dielectric constant and high thermal stability make this compound a candidate for use as a low-k material.

Designing Ultra Low-k Dielectric Materials for Ease of Patterning

2010 ◽  
Vol 1249 ◽  
Author(s):  
George Andrew Antonelli ◽  
Gengwei Jiang ◽  
Mandyam Sriram ◽  
Kaushik Chattopadhyay ◽  
Wei Guo ◽  
...  
Keyword(s):  
Inductively Coupled Plasma ◽  
Ion Beam ◽  
Plasma Reactor ◽  
Dielectric Materials ◽  
Dielectric Constants ◽  
Interlayer Dielectric ◽  
Inductively Coupled ◽  
Inductively Coupled Plasma Reactor ◽  
Low K

AbstractOrganosilicate materials with dielectric constants (k) ranging from 3.0 to 2.2 are in production or under development for use as interlayer dielectric materials in advanced interconnect logic technology. The dielectric constant of these materials is lowered through the addition of porosity which lowers the film density, making the patterning of these materials difficult. The etching kinetics and surface roughening of a series of low-k dielectric materials with varying porosity and composition were investigated as a function of ion beam angle in a 7% C4F8/Ar chemistry in an inductively-coupled plasma reactor. A similar set of low-k samples were patterned in a single damascene scheme. With a basic understanding of the etching process, we will show that it is possible to proactively design a low-k material that is optimized for a given patterning. A case study will be used to illustrate this point.

Siloxane Polymers as Low Dielectric Materials for Microelectronics

1995 ◽  
Vol 390 ◽  
Author(s):  
C. P. Wong
Keyword(s):  
Dielectric Constant ◽  
Three Dimensional ◽  
Signal Propagation ◽  
Dielectric Materials ◽  
Propagation Delay ◽  
Dimensional Structure ◽  
Low Dielectric Constant ◽  
Interlayer Dielectric ◽  
Low Dielectric ◽  
High Dielectric

ABSTRACTA modem VLSI device is a complicated three-dimensional structure that consists of multilayer metallization conductor lines which are separated with interlayer-dielectrics as insulation. This VLSI technology drives the IC device into sub-micron feature size that operates at ultra-fast speed (in excess of > 100 MHz). Passivation and interlayer dielectric materials are critical to the device performance due to the conductor signal propagation delay of the high dielectric constant of the material. Low dielectric constant materials are the preferred choice of materials for this reasons. These materials, such as Teflon® and siloxanes (silicones), are desirable because of their low dielectric constant (∈1) = 2.0, 2.7, respectively. This paper describes the use of a low dielectric constant siloxane polymer (silicone) as IC devices passivation layer material, its chemistry, material processes and reliability testing.

scholarly journals The Evolution of Organosilicon Precursors for Low-k Interlayer Dielectric Fabrication Driven by Integration Challenges

Materials ◽  
2021 ◽  
Vol 14 (17) ◽  
pp. 4827
Author(s):  
Nianmin Hong ◽  
Yinong Zhang ◽  
Quan Sun ◽  
Wenjie Fan ◽  
Menglu Li ◽  
...  
Keyword(s):  
Dielectric Constant ◽  
Data Storage ◽  
Integrated Circuit ◽  
Porous Silica ◽  
Dielectric Materials ◽  
Interlayer Dielectric ◽  
Damascene Process ◽  
Key Issues ◽  
Deposition Processes ◽  
Low K

Since the application of silicon materials in electronic devices in the 1950s, microprocessors are continuously getting smaller, faster, smarter, and larger in data storage capacity. One important factor that makes progress possible is decreasing the dielectric constant of the insulating layer within the integrated circuit (IC). Nevertheless, the evolution of interlayer dielectrics (ILDs) is not driven by a single factor. At first, the objective was to reduce the dielectric constant (k). Reduction of the dielectric constant of a material can be accomplished by selecting chemical bonds with low polarizability and introducing porosity. Moving from silicon dioxide, silsesquioxane-based materials, and silica-based materials to porous silica materials, the industry has been able to reduce the ILDs’ dielectric constant from 4.5 to as low as 1.5. However, porous ILDs are mechanically weak, thermally unstable, and poorly compatible with other materials, which gives them the tendency to absorb chemicals, moisture, etc. All these features create many challenges for the integration of IC during the dual-damascene process, with plasma-induced damage (PID) being the most devastating one. Since the discovery of porous materials, the industry has shifted its focus from decreasing ILDs’ dielectric constant to overcoming these integration challenges. More supplementary precursors (such as Si-C-Si structured compounds), deposition processes (such as NH3 plasma treatment), and post porosity plasma protection treatment (P4) were invented to solve integration-related challenges. Herein, we present the evolution of interlayer dielectric materials driven by the following three aspects, classification of dielectric materials, deposition methods, and key issues encountered and solved during the integration phase. We aim to provide a brief overview of the development of low-k dielectric materials over the past few decades.

High-Performance Vertical Gate-All-Around Silicon Nanowire FET With High- $\kappa $ /Metal Gate

2014 ◽  
Vol 61 (11) ◽  
pp. 3896-3900 ◽  
Author(s):  
Yujia Zhai ◽  
Leo Mathew ◽  
Rajesh Rao ◽  
Marylene Palard ◽  
Sonali Chopra ◽  
...  
Keyword(s):  
High Performance ◽  
Silicon Nanowire ◽  
Metal Gate

Novel Materials as Interlayer Low-K Dielectrics for CMOS Interconnect Applications

2011 ◽  
Vol 110-116 ◽  
pp. 5380-5383
Author(s):  
Tejas R. Naik ◽  
Veena R. Naik ◽  
Nisha P. Sarwade
Keyword(s):  
Dielectric Constant ◽  
Integrated Circuits ◽  
Dielectric Materials ◽  
Low Dielectric Constant ◽  
Interlayer Dielectric ◽  
Novel Materials ◽  
Low Dielectric ◽  
Processing Properties ◽  
New Generation ◽  
Low K

Scaling down the integrated circuits has resulted in the arousal of number of problems like interaction between interconnect, crosstalk, time delay etc. These problems can be overcome by new designs and by use of corresponding novel materials, which may be a solution to these problems. In the present paper we try to put forward very recent development in the use of novel materials as interlayer dielectrics (ILDs) having low dielectric constant (k) for CMOS interconnects. The materials presented here are porous and hybrid organo-inorganic new generation interlayer dielectric materials possessing low dielectric constant and better processing properties.

Process Integration issues for Interlevel Dielectric Materials for Sub-quarter Micron Silicon Integrated Circuits

1998 ◽  
Vol 511 ◽  
Author(s):  
Vijay Parihar ◽  
R. Singh
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
Process Integration ◽  
Dielectric Materials ◽  
New Approach ◽  
Interlayer Dielectric ◽  
Low Dielectric ◽  
Silicon Integrated Circuits ◽  
Processing Techniques ◽  
Low K

ABSTRACTThe continued miniaturization towards sub-quarter micron feature size mandates the search for low dielectric constant interlayer dielectric materials. A large number of materials and processing techniques has been suggested, but so far none of the proposed dielectric materials as well as processing techniques have been integrated into standard integrated circuit processing. In this paper, a new approach has been formulated for integration of low-k dielectric materials for future integrated circuits.

scholarly journals Enhanced performance of 19 single gate MOSFET with high permittivity dielectric material

2020 ◽  
Vol 18 (2) ◽  
pp. 724
Author(s):  
Ameer F. Roslan ◽  
F. Salehuddin ◽  
A. S. M. Zain ◽  
K. E. Kaharudin ◽  
I. Ahmad
Keyword(s):  
Performance Improvement ◽  
Dielectric Material ◽  
Dielectric Materials ◽  
Metal Gate ◽  
High Permittivity ◽  
Minimum Requirement ◽  
Technology Roadmap ◽  
High K ◽  
Low Performance ◽  
High K Dielectric

<p><span>In this research, the performance of the 19 nm single gate MOSFET is enhanced through the implementation of the high permittivity dielectric material. The MOSFET scaling trends necessities in device dimensions can be satisfied through the implementation of the high-K dielectric materials in place of the SiO2. Therefore, the 19 nm n-channel MOSFET device with different High-K dielectric materials are implemented and its performance improvement has also been analysed. Virtual fabrication is exercised through ATHENA module from Silvaco TCAD tool. Meanwhile, the device characteristic was utilized by using an ATLAS module. The aforementioned materials have also been simulated and compared with the conventional gate oxide SiO2 for the same structure. At the end, the results have proved that Titanium oxide (TiO2) device is the best dielectric material with a combination of metal gate Tungsten Silicides (WSix). The drive current (ION) of this device (WSix/TiO2) is 587.6 µA/um at 0.534 V of threshold voltage (VTH) as opposed to the targeted 0.530 V predicted, as well as a relatively low IOFF that is obtained at 1.92 pA/µm. This ION value meets the minimum requirement predicted by International Technology Roadmap for Semiconductor (ITRS) 2013 prediction for low performance <br /> (LP) technology. </span></p>

All-carbocycle hydrocarbon thermosets with high thermal stability and robust mechanical strength for low-k interlayer dielectrics

2021 ◽  
Author(s):  
Yudi Feng ◽  
Ke Jin ◽  
Jia Guo ◽  
Changchun Wang
Keyword(s):  
Thermal Stability ◽  
Mechanical Strength ◽  
Dielectric Materials ◽  
High Thermal Stability ◽  
Thermal Stabilities ◽  
Interlayer Dielectric ◽  
Interlayer Dielectrics ◽  
Low Permittivity ◽  
Low K

The development of modern microelectronic industry calls for low permittivity interlayer dielectric materials with excellent thermal stabilities, robust mechanical strength and matching processability. Traditionally, it is difficult to fabricate materials...

Sign in / Sign up

Export Citation Format

Share Document