scholarly journals III/V-on-Si MQW lasers by using a novel photonic integration method of regrowth on a bonding template

2019 ◽  
Vol 8 (1) ◽  
Author(s):  
Yingtao Hu ◽  
Di Liang ◽  
Kunal Mukherjee ◽  
Youli Li ◽  
Chong Zhang ◽  
...  

Abstract Silicon photonics is becoming a mainstream data-transmission solution for next-generation data centers, high-performance computers, and many emerging applications. The inefficiency of light emission in silicon still requires the integration of a III/V laser chip or optical gain materials onto a silicon substrate. A number of integration approaches, including flip-chip bonding, molecule or polymer wafer bonding, and monolithic III/V epitaxy, have been extensively explored in the past decade. Here, we demonstrate a novel photonic integration method of epitaxial regrowth of III/V on a III/V-on-SOI bonding template to realize heterogeneous lasers on silicon. This method decouples the correlated root causes, i.e., lattice, thermal, and domain mismatches, which are all responsible for a large number of detrimental dislocations in the heteroepitaxy process. The grown multi-quantum well vertical p–i–n diode laser structure shows a significantly low dislocation density of 9.5 × 104 cm−2, two orders of magnitude lower than the state-of-the-art conventional monolithic growth on Si. This low dislocation density would eliminate defect-induced laser lifetime concerns for practical applications. The fabricated lasers show room-temperature pulsed and continuous-wave lasing at 1.31 μm, with a minimal threshold current density of 813 A/cm2. This generic concept can be applied to other material systems to provide higher integration density, more functionalities and lower total cost for photonics as well as microelectronics, MEMS, and many other applications.

2012 ◽  
Vol 1396 ◽  
Author(s):  
Di Liang ◽  
John E. Bowers

ABSTRACTSilicon (Si) has been the dominating material platform of microelectronics over half century. Continuous technological advances in circuit design and manufacturing enable complementary metal-oxide semiconductor (CMOS) chips with increasingly high integration complexity to be fabricated in an unprecedently scale and economical manner. Conventional Si-based planar lightwave circuits (PLCs) has benefited from advanced CMOS technology but only demonstrate passive functionalities in most circumstances due to poor light emission efficiency and weak major electro-optic effects (e.g., Pockels effect, the Kerr effect and the Franz–Keldysh effect) in Si. Recently, a new hybrid III-V-on-Si integration platform has been developed, aiming to bridge the gap between Si and III-V direct-bandgap materials for active Si photonic integrated circuit applications. Since then high-performance lasers, amplifiers, photodetectors and modulators, etc. have been demonstrated. Here we review the most recent progress on hybrid Si lasers and high-speed hybrid Si modulators. The former include distributed feedback (DFB) lasers showing over 10 mW output power and up to 85 oC continuous-wave (cw) operation, compact hybrid microring lasers with cw threshold less than 4 mA and over 3 mW output power, and 4-channel hybrid Si AWG lasers with channel space of 360 GHz. Recently fabricated traveling-wave electro-absorption modulators (EAMs) and Mach-Zehnder interferometer modulators (MZM) on this platform support 50 Gb/s and 40 Gb/s data transmission with over 10 dB extinction ratio, respectively.


2001 ◽  
Vol 693 ◽  
Author(s):  
Takeharu Asano ◽  
Motonobu Takeya ◽  
Tsuyoshi Tojyo ◽  
Shinro Ikeda ◽  
Takashi Mizuno ◽  
...  

AbstractHigh-power AlGaInN-based laser diodes (LDs) operating with high reliability in the 400-nm band have been successfully fabricated using a high-productivity process. Epitaxial lateral overgrowth (ELO) over a 10-m m region was employed to obtain a broad growth area with low dislocation density, and the thickness of the ELO-GaN layer was limited to approximately 5 m in order to minimize wafer bending. These techniques allow for the easy and reproducible alignment of the laser stripe on the region of low dislocation density. The insertion of a GaInN interlayer between the active layer and the AlGaN electron blocking layer was effective for reducing the strain between these two layers, resulting in homogeneous luminescence from the active layer and lower operating current. A mean time to failure of 15000 h under 30-mW continuous-wave operation at 60°C was realized as a direct result of the lower operating current. Productivity was remarkably improved by performing epitaxial growth on a 3-inch substrate. Highly uniform laser wafers were successfully fabricated by achieving minimal temperature variation (1000 ±7°C) over the 3-inch substrate. The resultant laser structures varied in thickness by only ±5%, and the photoluminescence wavelength was consistent within ±2.5 nm over the entire 3-inch substrate. The average threshold current of 550 LDs selected from a fourth wafer was 32.7 mA, with small standard deviation of 3.2 mA.


2019 ◽  
Vol 10 (1) ◽  
Author(s):  
Youcef A. Bioud ◽  
Abderraouf Boucherif ◽  
Maksym Myronov ◽  
Ali Soltani ◽  
Gilles Patriarche ◽  
...  

Abstract The monolithic integration of III-V compound semiconductor devices with silicon presents physical and technological challenges, linked to the creation of defects during the deposition process. Herein, a new defect elimination strategy in highly mismatched heteroepitaxy is demonstrated to achieve a ultra-low dislocation density, epi-ready Ge/Si virtual substrate on a wafer scale, using a highly scalable process. Dislocations are eliminated from the epilayer through dislocation-selective electrochemical deep etching followed by thermal annealing, which creates nanovoids that attract dislocations, facilitating their subsequent annihilation. The averaged dislocation density is reduced by over three orders of magnitude, from ~108 cm−2 to a lower-limit of ~104 cm−2 for 1.5 µm thick Ge layer. The optical properties indicate a strong enhancement of luminescence efficiency in GaAs grown on this virtual substrate. Collectively, this work demonstrates the promise for transfer of this technology to industrial-scale production of integrated photonic and optoelectronic devices on Si platforms in a cost-effective way.


2004 ◽  
Vol 03 (01n02) ◽  
pp. 187-192
Author(s):  
G. LIN ◽  
I. F. CHEN ◽  
F. J. LAY ◽  
J. Y. CHI ◽  
D. A. LIVSHITS ◽  
...  

We have investigated light-current and spectral characteristics of 2-, 5- and 10-stack InAs / InGaAs / GaAs quantum dot (QD) ridge-waveguide lasers grown by MBE. Ultra-low threshold current of 1.43 mA was achieved for 2-stack QD laser. Simultaneous lasing at ground- and excited-states was observed. This effect is accounted for the finite time of carriers capture to the ground-state in QDs. Multi-stack QD structures enables to maintain continuous-wave (CW) ground-state lasing up to the current density of 100×Jth and to achieve the highest output power and efficiency ever recorded for any single-mode lasers of 1.3-μm-wavelength range.


2021 ◽  
Vol 42 (11) ◽  
pp. 112301
Author(s):  
Teng Fei ◽  
Shenqiang Zhai ◽  
Jinchuan Zhang ◽  
Ning Zhuo ◽  
Junqi Liu ◽  
...  

Abstract Robust quantum cascade laser (QCL) enduring high temperature continuous-wave (CW) operation is of critical importance for some applications. We report on the realization of lattice-matched InGaAs/InAlAs/InP QCL materials grown by metal-organic chemical vapor deposition (MOCVD). High interface quality structures designed for light emission at 8.5 μm are achieved by optimizing and precise controlling of growth conditions. A CW output power of 1.04 W at 288 K was obtained from a 4 mm-long and 10 μm-wide coated laser. Corresponding maximum wall-plug efficiency and threshold current density were 7.1% and 1.18 kA/cm2, respectively. The device can operate in CW mode up to 408 K with an output power of 160 mW.


Author(s):  
Yoav Weizman ◽  
Ezra Baruch

Abstract In recent years, two new techniques were introduced for flip chip debug; the Laser Voltage Probing (LVP) technique and Time Resolved Light Emission Microscopy (TRLEM). Both techniques utilize the silicon’s relative transparency to wavelengths longer than the band gap. This inherent wavelength limitation, together with the shrinking dimensions of modern CMOS devices, limit the capabilities of these tools. It is known that the optical resolution limits of the LVP and TRLEM techniques are bounded by the diffraction limit which is ~1um for both tools using standard optics. This limitation was reduced with the addition of immersion lens optics. Nevertheless, even with this improvement, shrinking transistor geometry is leading to increased acquisition time, and the overlapping effect between adjacent nodes remains a critical issue. The resolution limit is an order of magnitude above the device feature densities in the < 90nm era. The scaling down of transistor geometry is leading to the inevitable consequence where more than 50% of the transistors in 90nm process have widths smaller than 0.4um. The acquisition time of such nodes becomes unreasonably long. In order to examine nodes in a dense logic cuicuit, cross talk and convolution effects between neighboring signals also need to be considered. In this paper we will demonstrate the impact that these effects may have on modern design. In order to maintain the debug capability, with the currently available analytical tools for future technologies, conceptual modification of the FA process is required. This process should start on the IC design board where the VLSI designer should be familiar with FA constraints, and thus apply features that will enable enhanced FA capabilities to the circuit in hand during the electrical design or during the physical design stages. The necessity for reliable failure analysis in real-time should dictate that the designer of advanced VLSI blocks incorporates failure analysis constraints among other design rules. The purpose of this research is to supply the scientific basis for the optimal incorporation of design rules for optical probing in the < 90nm gate era. Circuit designers are usually familiar with the nodes in the design which are critical for debug, and the type of measurement (logic or DC level) they require. The designer should enable the measurement of these signals by applying certain circuit and physical constraints. The implementation of these constraints may be done at the cell level, the block level or during the integration. We will discuss the solutions, which should be considered in order to mitigate tool limitations, and also to enable their use for next generation processes.


2020 ◽  
Vol 13 (9) ◽  
pp. 095501
Author(s):  
Ding Wang ◽  
Kenjiro Uesugi ◽  
Shiyu Xiao ◽  
Kenji Norimatsu ◽  
Hideto Miyake

Crystals ◽  
2021 ◽  
Vol 11 (3) ◽  
pp. 235
Author(s):  
Shuqi Zhao ◽  
Tongtong Yu ◽  
Ziming Wang ◽  
Shilei Wang ◽  
Limei Wei ◽  
...  

Two-dimensional (2D) materials driven by their unique electronic and optoelectronic properties have opened up possibilities for their various applications. The large and high-quality single crystals are essential to fabricate high-performance 2D devices for practical applications. Herein, IV-V 2D GeP single crystals with high-quality and large size of 20 × 15 × 5 mm3 were successfully grown by the Bi flux growth method. The crystalline quality of GeP was confirmed by high-resolution X-ray diffraction (HRXRD), Laue diffraction, electron probe microanalysis (EPMA) and Raman spectroscopy. Additionally, intrinsic anisotropic optical properties were investigated by angle-resolved polarized Raman spectroscopy (ARPRS) and transmission spectra in detail. Furthermore, we fabricated high-performance photodetectors based on GeP, presenting a relatively large photocurrent over 3 mA. More generally, our results will significantly contribute the GeP crystal to the wide optoelectronic applications.


Nanophotonics ◽  
2021 ◽  
Vol 0 (0) ◽  
Author(s):  
Shaoni Kar ◽  
Nur Fadilah Jamaludin ◽  
Natalia Yantara ◽  
Subodh G. Mhaisalkar ◽  
Wei Lin Leong

Abstract Perovskite semiconductors have experienced meteoric rise in a variety of optoelectronic applications. With a strong foothold on photovoltaics, much focus now lies on their light emission applications. Rapid progress in materials engineering have led to the demonstration of external quantum efficiencies that surpass the previously established theoretical limits. However, there remains much scope to further optimize the light propagation inside the device stack through careful tailoring of the optical processes that take place at the bulk and interface levels. Photon recycling in the emitter material followed by efficient outcoupling can result in boosting external efficiencies up to 100%. In addition, the poor ambient and operational stability of these materials and devices restrict further commercialization efforts. With best operational lifetimes of only a few hours reported, there is a long way to go before perovskite LEDs can be perceived as reliable alternatives to more established technologies like organic or quantum dot-based LED devices. This review article starts with the discussions of the mechanism of luminescence in these perovskite materials and factors impacting it. It then looks at the possible routes to achieve efficient outcoupling through nanostructuring of the emitter and the substrate. Next, we analyse the instability issues of perovskite-based LEDs from a photophysical standpoint, taking into consideration the underlying phenomena pertaining to defects, and summarize recent advances in mitigating the same. Finally, we provide an outlook on the possible routes forward for the field and propose new avenues to maximally exploit the excellent light-emitting capabilities of this family of semiconductors.


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