scholarly journals Self-selective ferroelectric memory realized with semimetalic graphene channel

2021 ◽  
Vol 5 (1) ◽  
Author(s):  
Sungchul Jung ◽  
Jinyoung Park ◽  
Junhyung Kim ◽  
Wonho Song ◽  
Jaehyeong Jo ◽  
...  
Keyword(s):  
High Speed ◽  
Random Access ◽  
Memory State ◽  
Cross Point ◽  
Ultra Low Power ◽  
Ferroelectric Layer ◽  
Non Volatile Memory ◽  
Long Lifetime ◽  
Effect Transistor ◽  
Ferroelectric Memory

AbstractA new concept of read-out method for ferroelectric random-access memory (FeRAM) using a graphene layer as the channel material of bottom-gated field effect transistor structure is demonstrated experimentally. The transconductance of the graphene channel is found to change its sign depending on the direction of spontaneous polarization (SP) in the underlying ferroelectric layer. This indicates that the memory state of FeRAM, specified by the SP direction of the ferroelectric layer, can be sensed unambiguously with transconductance measurements. With the proposed read-out method, it is possible to construct an array of ferroelectric memory cells in the form of a cross-point structure where the transconductance of a crossing cell can be measured selectively without any additional selector. This type of FeRAM can be a plausible solution for fabricating high speed, ultra-low power, long lifetime, and high density 3D stackable non-volatile memory.

scholarly journals Challenges and Applications of Emerging Nonvolatile Memory Devices

Electronics ◽  
2020 ◽  
Vol 9 (6) ◽  
pp. 1029 ◽  
Author(s):  
Writam Banerjee
Keyword(s):  
Nonvolatile Memory ◽  
High Speed ◽  
Low Voltage ◽  
Random Access ◽  
Random Access Memory ◽  
Spin Transfer Torque ◽  
High Density ◽  
Memory Storage ◽  
Access Memory ◽  
Ultra Low Power

Emerging nonvolatile memory (eNVM) devices are pushing the limits of emerging applications beyond the scope of silicon-based complementary metal oxide semiconductors (CMOS). Among several alternatives, phase change memory, spin-transfer torque random access memory, and resistive random-access memory (RRAM) are major emerging technologies. This review explains all varieties of prototype and eNVM devices, their challenges, and their applications. A performance comparison shows that it is difficult to achieve a “universal memory” which can fulfill all requirements. Compared to other emerging alternative devices, RRAM technology is showing promise with its highly scalable, cost-effective, simple two-terminal structure, low-voltage and ultra-low-power operation capabilities, high-speed switching with high-endurance, long retention, and the possibility of three-dimensional integration for high-density applications. More precisely, this review explains the journey and device engineering of RRAM with various architectures. The challenges in different prototype and eNVM devices is disused with the conventional and novel application areas. Compare to other technologies, RRAM is the most promising approach which can be applicable as high-density memory, storage class memory, neuromorphic computing, and also in hardware security. In the post-CMOS era, a more efficient, intelligent, and secure computing system is possible to design with the help of eNVM devices.

A Novel Design of High Performance and Robust Ultra-Low Power SRAM Cell Based on Memcapacitor

2021 ◽  
Author(s):  
Alireza Abbasi ◽  
Farbod Setoudeh ◽  
Mohammad Bagher Tavakoli ◽  
Ashkan Horri
Keyword(s):  
Power Consumption ◽  
High Performance ◽  
Random Access ◽  
Access Memory ◽  
Ultra Low Power ◽  
Cell Parameters ◽  
Consumption Data ◽  
Sram Cell ◽  
Non Volatile Memory ◽  
Novel Design

Abstract The present paper proposes a six-FinFET two-memcapacitor (6T2MC) non-volatile static random-access memory (NVSRAM). In this design, the two memcapacitors are used as non-volatile memory elements. The proposed cell is flexible against data loss when turned off and offers significant improvement in read and write operations compared to previous NVSRAMs. The performance of the new NVSRAM design is evaluated in terms of read and write operation at particular nanometric feature sizes. Moreover, the proposed 6T2MC cell is compared with 8T2R, 8T1R, 7T1R, and 7T2R cells. The results show that 6T2MC has a 5.50% lower write delay and 98.35% lower read delay compared to 7T2R and 7T1R cells, respectively. The 6T2MC cell exhibits 38.86% lower power consumption and 23.80% lower leakage power than 7T2R and 7T1R cells. The proposed cell is significantly improved in terms of HSNM, RSNM, and WSNM compared to 8T2R, 8T1R, 7T2R, and 7T1R cells, respectively. Important cell parameters, such as power consumption, data read/write delay, and SNM, are significantly improved. The superior characteristics of FinFET over MOSFET and the combination of this technology with memcapacitors lead to significant improvement in the proposed design.

scholarly journals Influence of Domain Structure in Ferroelectric Substrate on Graphene Conductance (Authors' Review)

2018 ◽  
Vol 63 (1) ◽  
pp. 49 ◽  
Author(s):  
M. V. Strikha ◽  
A. I. Kurchak ◽  
A. N. Morozovska
Keyword(s):  
Domain Structure ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Random Access ◽  
Analytical Description ◽  
Localized States ◽  
Ferroelectric Domain Structure ◽  
Effect Transistor ◽  
Ferroelectric Memory ◽  
The Impact

Review is devoted to the recent theoretical studies of the impact of domain structure of ferroelectric substrate on graphene conductance. An analytical description of the hysteresis memory effect in a field effect transistor based on graphene-on-ferroelectric, taking into account absorbed dipole layers on the free surface of graphene and localized states on its interfaces is considered. The aspects of the recently developed theory of p-n junctions conductivity in a graphene channel on a ferroelectric substrate, which are created by a 180-degree ferroelectric domain structure, are analyzed, and cases of different current regimes from ballistic to diffusion one are considered. The influence of size effects in such systems and the possibility of using the results for improving the characteristics of field effect transistors with a graphene channel, non-volatile ferroelectric memory cells with random access, sensors, as well as for miniaturization of various devices of functional nanoelectronics are discussed.

scholarly journals Ferroelectric memory: state-of-the-art manufacturing and research

2020 ◽  
Vol 8 (5) ◽  
pp. 44-67
Author(s):  
D. A. Abdullaev ◽  
R. A. Milovanov ◽  
R. L. Volkov ◽  
N. I. Borgardt ◽  
A. N. Lantsev ◽  
...  
Keyword(s):  
Lead Zirconate Titanate ◽  
High Speed ◽  
New Technologies ◽  
State Of The Art ◽  
Semiconductor Industry ◽  
Cmos Process ◽  
Memory Cells ◽  
Memory State ◽  
Emerging Memory ◽  
Ferroelectric Memory

Semiconductor industry calls for emerging memory, demonstrating high speed (like SRAM or DRAM), nonvolatility (like Flash NAND), high endurance and density, good scalability, reduced energy consumption and reasonable cost. Ferroelectric memory FRAM has been considered as one of the emerging memory technologies for over 20 years. FRAM uses polarization switching that provides low power consumption, nonvolatility, high speed and endurance, robust data retention, and resistance to data corruption via electric, magnetic fields and radiation. Despite the advantages, market share held by FRAM manufacturers is insignificant due to scaling challenges. State-of-the-art FRAM manufacturing is studied in this paper. Ferroelectric capacitors and memory cells made by main commercial FRAM manufactures (Texas Instruments, Cypress Semiconductor, Fujitsu и Lapis Semiconductor) are explored. All memory cells are based on the lead zirconate titanate PZT capacitor with the thickness of about 70 nm and IrOx/Ir or Pt electrodes. The leading FRAM technology remains the 130 nm node CMOS process developed at Texas Instruments fabs. New approaches to further scaling and new devices based on ferroelectrics are reviewed, including binary ferroelectrics deposited by ALD techniques, piezoelectronic transistors, ferroelectric/2D-semiconductor transistor structures, and others. Whether FRAM technology will be able to resolve one of the main contradictions between a high-speed processor and a relatively slow nonvolatile memory depends on the success of the new technologies integration.

Performance Evaluation of Negative-Capacitance Fin-Type Field Effect Transistor-Based Static Random-Access Memory with Mixed-Mode Simulation

2021 ◽  
Vol 16 (3) ◽  
pp. 414-419
Author(s):  
Xianlong Chen ◽  
Weifeng Lü ◽  
Bo Liu ◽  
Tiejun Du ◽  
Mi Lin
Keyword(s):  
Mixed Mode ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Random Access ◽  
Random Access Memory ◽  
Static Random Access Memory ◽  
Negative Capacitance ◽  
Access Memory ◽  
Ferroelectric Layer ◽  
Effect Transistor

Electrical characteristics of fin-type field-effect transistor with negative capacitance effect (NCFinFET) are investigated coupled with the Landau-Khalatnikov equation for ferroelectric materials in this study. Moreover, Technology Computer Aided Design (TCAD) mixed-mode simulation is carried out to evaluate and compare the performance of NCFinFET-based static random access memory cell (NC-SRAM) with a traditional FinFETbased SRAM one. It is shown NC-SRAM has higher static noise margin (SNM) and better anti-interference capability than conventional SRAM with the same supply voltage. The static read, hold, and write noise margins (RSNM, HSNM, and WSNM, respectively) for NC-SRAM increased by 10%, 30%, and 15%, respectively, and the access disturb stability improved by 80%. Simulation results also reveal that the read stability increases with increasing ferroelectric layer thickness, while the write stability exhibits a non-monotonic trend with ferroelectric layer thickness for NC-SRAM.

Reproducible Resistance Switching in Ni/NiO/Ni Trilayer

2007 ◽  
Vol 997 ◽  
Author(s):  
Hisashi Shima ◽  
Fumiyoshi Takano ◽  
Hiro Akinaga ◽  
Isao H Inoue ◽  
Hidenori Takagi
Keyword(s):  
Thin Film ◽  
High Speed ◽  
Random Access ◽  
Random Access Memory ◽  
Resistance Switching ◽  
Access Memory ◽  
Pt Electrode ◽  
Resistance Random Access Memory ◽  
Nio Thin Film ◽  
Non Volatile Memory

AbstractThe resistance random access memory is attracting much attention as a high-density and high-speed non-volatile memory, having large resistance switching ration and good affinity with the conventional CMOS technologies. We demonstrate the resistance switching in the NiO thin film without using Pt electrode.

scholarly journals Energy-Efficient Non-Von Neumann Computing Architecture Supporting Multiple Computing Paradigms for Logic and Binarized Neural Networks

2021 ◽  
Vol 11 (3) ◽  
pp. 29
Author(s):  
Tommaso Zanotti ◽  
Francesco Maria Puglisi ◽  
Paolo Pavan
Keyword(s):  
Neural Networks ◽  
High Performance ◽  
Random Access ◽  
Resistive Random Access Memory ◽  
Hardware Accelerators ◽  
Memory Architecture ◽  
Ultra Low Power ◽  
Von Neumann ◽  
Non Volatile Memory ◽  
Volatile Memory

Different in-memory computing paradigms enabled by emerging non-volatile memory technologies are promising solutions for the development of ultra-low-power hardware for edge computing. Among these, SIMPLY, a smart logic-in-memory architecture, provides high reconfigurability and enables the in-memory computation of both logic operations and binarized neural networks (BNNs) inference. However, operation-specific hardware accelerators can result in better performance for a particular task, such as the analog computation of the multiply and accumulate operation for BNN inference, but lack reconfigurability. Nonetheless, a solution providing the flexibility of SIMPLY while also achieving the high performance of BNN-specific analog hardware accelerators is missing. In this work, we propose a novel in-memory architecture based on 1T1R crossbar arrays, which enables the coexistence on the same crossbar array of both SIMPLY computing paradigm and the analog acceleration of the multiply and accumulate operation for BNN inference. We also highlight the main design tradeoffs and opportunities enabled by different emerging non-volatile memory technologies. Finally, by using a physics-based Resistive Random Access Memory (RRAM) compact model calibrated on data from the literature, we show that the proposed architecture improves the energy delay product by >103 times when performing a BNN inference task with respect to a SIMPLY implementation.

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