Reduction in components using modified topology for asymmetrical multilevel inverter

2019 ◽  
Vol 16 (1) ◽  
pp. 71-77 ◽  
Author(s):  
Kanungo Barada Mohanty ◽  
Kishor Thakre ◽  
Aditi Chatterjee ◽  
Ashwini Kumar Nayak ◽  
Vinaya Sagar Kommukuri
Keyword(s):  
Pulse Width Modulation ◽  
Multilevel Inverter ◽  
Modulation Scheme ◽  
Content Type ◽  
Basic Module ◽  
Experimental Implementation ◽  
Blocking Voltage ◽  
Comparison Results ◽  
Main Emphasis ◽  
Gate Driver

Purpose This study aims to propose a modified topology for an asymmetric multilevel inverter as a basic module that generates 13-level output voltage waveform. The basic module consists of eight switches (unidirectional and bidirectional switch) and four DC voltage sources with unequal magnitudes. The proposed topology reduces the number of switches, isolated DC sources, cost and size of the circuit significantly as compared to other topologies. In addition, the proposed circuit provides a modular structure for a multilevel inverter. Design/methodology/approach The proposed configuration is implemented through simulation and hardware development of a single-phase 13-level inverter prototype. A multicarrier-based pulse width modulation scheme is adopted for generating switching signals by using dSPACE real-time controller. Findings To demonstrate the advantages of the proposed configuration, a comparative analysis is carried out with other multilevel topologies in terms of number of switches, gate driver circuits, on-state switches and blocking voltage on the switches. The comparison results confirmed that the proposed configuration requires less number of components for the same number of voltage levels. Moreover, the peak inverse voltage on switches and losses is lower in the proposed configuration. Originality/value In the available literature, numerous topologies are presented with main emphasis on the reduced components count. In this study, the authors proposed a new topology for an asymmetrical source configuration. The performance of the proposed topology under steady-state and dynamic conditions is evaluated using simulation and experimental implementation.

Component Count Reduced, Filter-Less H-Bridge Multilevel Inverter with Series and Parallel Connected Switches

2020 ◽  
pp. 2150052
Author(s):  
M Vijayakumar ◽  
S. M. Ramesh
Keyword(s):  
Pulse Width Modulation ◽  
Harmonic Distortion ◽  
Sine Wave ◽  
Multilevel Inverter ◽  
Level Shift ◽  
Modulation Scheme ◽  
Power Switching ◽  
Power Switches ◽  
Driver Circuit ◽  
Gate Driver

This paper introduces a new premium multilevel inverter (MLI) topology with cascaded H-Bridge and series-parallel connected switches to synthesize the fundamental sine wave with various levels of voltage. The component count is decreased by reducing the number of power switching devices, optoisolators, voltage gate drivers, snubber and filter circuits. The combination of two power switches and a separated DC (SDC) source is called an SDC module. Five SDC modules are required for a 63-level MLI and six SDC modules are required for a 127-level MLI. In this paper, both a 63-level and a 127-level filter-less single-phase MLIs are deliberated. The switches are controlled by employing a newer pulse width modulation (PWM) technique called periodic reduced digital carrier level shift PWM (PRDCLSPWM). As the number of levels increases to a greater extent, the total harmonic distortion diminishes without the need of filter circuit and the performance level also increases. Comparative analysis of proposed 63-level and 127-level MLIs topology with the conventional and modern topologies has been presented in terms of power switches, gate driver circuit requirement, DC voltage sources and THD limits. PRDCLSPWM scheme is derived and analyzed for the proposed 63-level and 127-level MLIs to eliminate low-order and high-order harmonics. Moreover, the performance of the proposed modulation scheme is compared with the most commonly used schemes. The modeling and simulation are done with MATLAB/SIMULINK 2016a.

New Topology for Asymmetrical Multilevel Inverter: An Effort to Reduced Device Count

2017 ◽  
Vol 27 (04) ◽  
pp. 1850055 ◽  
Author(s):  
Kishor Thakre ◽  
Kanungo Barada Mohanty ◽  
Vinaya Sagar Kommukuri ◽  
Aditi Chatterjee
Keyword(s):  
Output Voltage ◽  
Pulse Width Modulation ◽  
Harmonic Distortion ◽  
Multilevel Inverter ◽  
Dc Voltage ◽  
Experimental Implementation ◽  
Voltage Stress ◽  
Power Switches ◽  
Driver Circuit ◽  
Gate Driver

Nowadays, multilevel inverters (MLI) are receiving remarkable attention due to salient features like less voltage stress on switches and low total harmonic distortion (THD) in output voltage. However, the required switch count increases with number of voltage levels. This paper presents a new topology for asymmetric multilevel inverter as a fundamental block. Each block generates 13-level output voltage using eight switches and four unequal dc voltage sources. The proposed configuration offers special features such as reduced number of switches, isolated dc sources, cost economy, less complex and modular structure than other similar contemporary topologies. Moreover, significant reduction in voltage stress on the circuit switches can be achieved. Comparative studies of proposed topology with the conventional and recent topologies have been presented in terms of power switches, gate driver circuit requirement, isolated dc voltage sources and total standing voltage. Multicarrier-based sinusoidal pulse width modulation (SPWM) scheme is adopted for generating switching signals using dSPACE real-time controller. In addition, proposed topology offers a fewer number of ON-state switches that lead to reduction in power loss. The proposed topology is validated through simulation and experimental implementation.

scholarly journals Experimental validation of new self-voltage balanced 9L-ANPC inverter for photovoltaic applications

2021 ◽  
Vol 11 (1) ◽  
Author(s):  
M. Jagabar Sathik ◽  
Dhafer J. Almakhles ◽  
N. Sandeep ◽  
Marif Daula Siddique
Keyword(s):  
Output Voltage ◽  
Pulse Width Modulation ◽  
Superior Performance ◽  
Modulation Scheme ◽  
Switching Frequency ◽  
Switched Capacitor ◽  
Renewable Energy Resources ◽  
High Quality ◽  
Multilevel Inverters ◽  
Blocking Voltage

AbstractMultilevel inverters play an important role in extracting the power from renewable energy resources and delivering the output voltage with high quality to the load. This paper proposes a new single-stage switched capacitor nine-level inverter, which comprises an improved T-type inverter, auxiliary switch, and switched cell unit. The proposed topology effectively reduces the DC-link capacitor voltage and exhibits superior performance over recently switched-capacitor inverter topologies in terms of the number of power components and blocking voltage of the switches. A level-shifted multilevel pulse width modulation scheme with a modified triangular carrier wave is implemented to produce a high-quality stepped output voltage waveform with low switching frequency. The proposed nine-level inverter’s effectiveness, driven by the recommended modulation technique, is experimentally verified under varying load conditions. The power loss and efficiency for the proposed nine-level inverter are thoroughly discussed with different loads.

Simulation and Analysis of Novel Extendable Multilevel Inverter Topology

2019 ◽  
Vol 28 (06) ◽  
pp. 1950089 ◽  
Author(s):  
V. Thiyagarajan ◽  
P. Somasundaram ◽  
K. Ramash Kumar
Keyword(s):  
Single Phase ◽  
Harmonic Distortion ◽  
Multilevel Inverter ◽  
Voltage Waveform ◽  
Dc Voltage ◽  
Switching Losses ◽  
Comparison Results ◽  
Symmetrical Condition ◽  
Gate Driver ◽  
Inverter Topology

Multilevel inverter (MLI) has become more popular in high power, high voltage industries owing to its high quality output voltage waveform. This paper proposes a novel single phase extendable type MLI topology. The term ‘extendable’ is included since the presented topology can be extended with maximum number of dc voltage sources to synthesize larger output levels. This topology can be operated in both symmetrical and asymmetrical conditions. The major advantages of the proposed inverter topology include minimum switching components, reduced gate driver circuits, less harmonic distortion and reduced switching losses. The comparative analysis based on the number of switches, dc voltage sources and conduction switches between the proposed topology and other existing topologies is presented in this paper. The comparison results show that the proposed inverter topology requires fewer components. The performance of the proposed MLI topology has been analyzed in both symmetrical and asymmetrical conditions. The simulation model is developed using MATLAB/SIMULINK software to verify the performance of the proposed inverter topology and also the feasibility of the presented topology during the symmetrical condition has been validated experimentally.

Improved pulse‐width modulation scheme for T‐type multilevel inverter

2017 ◽  
Vol 10 (8) ◽  
pp. 968-976 ◽  
Author(s):  
Hari Priya Vemuganti ◽  
Dharmavarapu Sreenivasarao ◽  
Ganjikunta Siva Kumar
Keyword(s):  
Pulse Width ◽  
Pulse Width Modulation ◽  
Multilevel Inverter ◽  
Modulation Scheme

scholarly journals Power Quality Improvement in Modular Multilevel Inverter Using for Different Multicarrier PWM

2021 ◽  
Vol 5 (2) ◽  
pp. 19-27
Author(s):  
Thenmalar Kaliannan ◽  
Johny Renoald Albert ◽  
D. Muhamadha Begam ◽  
P. Madhumathi
Keyword(s):  
Power Quality ◽  
Pulse Width ◽  
Output Voltage ◽  
Pulse Width Modulation ◽  
Analog Circuit ◽  
Reactive Power ◽  
Pso Algorithm ◽  
Multilevel Inverter ◽  
Modulation Scheme ◽  
Non Linear Load

Pulse width modulation (PWM) is a powerful technique employed in analog circuit convert with a microprocessor based digital output. Besides, Pseudo Random Multi Carrier (PRMC) involves in two random PWM strategies to minimize the harmonic order for 9- level cascaded multilevel H-bridge (CHB) inverter and 9-level Modular Multilevel inverter are introduced. The design mainly focuses on the (Pulse Width Modulation) PWM method, in which two nearest voltage levels are approached in estimated output voltage prediction based on the Partial swarm optimization (PSO) algorithm, and it conveys a random variation in the pulse position of output by Pseudo Random Multi Carrier- Pulse Width Modulation (PRMC-PWM). The CHB and the Modular inverters generate low distortion output by using PMRC. The simulation and prototype circuit are developed for the nine level output using sixteen switches and ten with Resistive-Inductive (R-L) load variation condition. The power quality is improved in CHB and Modular inverter (MoI) with minimized harmonics in various modulation index (MI) as varied from 0.1 up to 0.8. The circuit is designed by using a Field Programmable Gate Array (FPGA), Implementing a PSO algorithm for both CHB, and MoI are proposed. The comparisons of results are verified with lower order harmonics and find the best switching angle across the MLI switches. Modular inverter furthermore investigates with PRMC, Random Nearest level (RNL) modulation scheme are presented, and the proposed circuit is along with the respective degree of the output voltage were synthesized in non-linear load by the development of reactive power across a motor load.

scholarly journals Performance Evaluation of Cascaded and Reduced Switch Multilevel Inverter Using Modified Carrier Based PWM Technique

2020 ◽  
Vol 6 (1) ◽  
pp. 12-19
Author(s):  
Md Tariqul Islam ◽  
Md Fayzur Rahman ◽  
AA Md Monzur Ul Akhir ◽  
Zisun Ahmed
Keyword(s):  
Pulse Width ◽  
Pulse Width Modulation ◽  
Harmonic Distortion ◽  
Multilevel Inverter ◽  
Modulation Scheme ◽  
Switching Loss ◽  
Quality Performance ◽  
Triangular Wave ◽  
Switching Losses ◽  
Control Scheme

This paper proposes an improved harmonic distorted modified triangular carrier-based multicarrier pulse width modulation for generating the switching pulses of a multilevel inverter. This modified triangular wave consists of a triangular wave bearing a close resemblance to an ‘M’ shaped wave. The design of this carrier signal has been optimized to maintain a low level of total harmonic distortion (THD), while increasing the fundamental o/p voltage to ensure the effective DC voltage utilization. Moreover, this optimization reduces the switching losses and improve the efficiency of the power inverter. With the help of this carrier signal, High-frequency alternative phase opposition disposition pulse width modulation (APODPWM) is generated. This new control scheme has been applied to seven levels of conventional cascaded H-bridge with reduced switch multilevel inverter. The output is compared with conventional carrier-based APODPWM. The comparison is made in terms of THD, fundamental output voltages and inverter losses. To ensure quality performance, conventional carrier and modified carrier-based multicarrier PWM topologies are used for the Cascaded seven-level inverter with reduced switch seven-level inverter having a carrier frequency of 2 kHz and modulation index of 0.8-1.30. According to the simulation results, by using the proposed modulation scheme the THD and the switching loss were reduced by 9.64[%] and 4.2[%] respectively. Besides, the proposed modulation technique increases the fundamental output voltages. The total simulation process is done in MATLAB Simulink environment. GUB JOURNAL OF SCIENCE AND ENGINEERING, Vol 6(1), Dec 2019 P 12-19

Integrated DC-AC and AC-DC converter using H-converter for wide range voltage applications

Circuit World ◽  
2021 ◽  
Vol ahead-of-print (ahead-of-print) ◽  
Author(s):  
Saravanan R. ◽  
Vijayshankar S. ◽  
Sathyaseelan Sathyaseelan ◽  
Suresh K.
Keyword(s):  
Pulse Width ◽  
Power Loss ◽  
Pulse Width Modulation ◽  
Modulation Scheme ◽  
Power Losses ◽  
Content Type ◽  
One Stage ◽  
Energy Storage Application ◽  
Wide Range ◽  
Zero Sequence

Purpose This paper aims to propose Hidden Converter (H-Converter) combined with dual port 3Ø inverter for energy storage application to produce wide range of voltage. Some of the application required wide range of voltages, but problem from E-chopper is either boost or buck mode of operations, both modes are not possible. To overcome this drawback, H-Converter is combined with dual port 3Ø inverter controlled by carrier-based pulse width modulation (CB-PWM) technique is added with zero sequence injection. Design/methodology/approach Hidden converter is a bidirectional DC-DC chopper used to convert fixed DC to variable DC and vice versa in both buck and boost modes of operations. Dual port inverter is combined with hidden DC-DC converter can produce wide range of voltages. Findings The bidirectional DC-AC converter requires less power for processing and consumes less power losses by using modest carrier built- pulse width modulation scheme through proposed zero structure addition. Originality/value By using this proposed strategy H-Converter can produce wide range of voltage in both the sides and mostly power is processed in the 3Ø inverter with a one stage conversion with less power loss. As a result, with one stage power conversion has more efficiency because of less power loss. This proposed converter has designed by analysis, and the real time result is tested in an experiment.

scholarly journals A novel single-phase PWM asymmetrical multilevel inverter with number of semiconductor switches reduction

2019 ◽  
Vol 10 (3) ◽  
pp. 1133
Author(s):  
S. Kakar ◽  
S. M. Ayob ◽  
N. M. Nordin ◽  
M. S. Arif ◽  
A. Jusoh ◽  
...  
Keyword(s):  
Single Phase ◽  
Pulse Width Modulation ◽  
Multilevel Inverter ◽  
Semiconductor Switches ◽  
Voltage Stress ◽  
Gate Driver ◽  
Inverter Topology ◽  
Sinusoidal Pulse Width Modulation ◽  
Lower Voltage ◽  
Fundamental Module

In this paper, a new asymmetrical multilevel inverter topology (MLI) is proposed with the objectives of using decreased number of semiconductor switches, dc voltage sources, gate driver circuits and dc links. The structure of presented MLI is very simple and modular. The fundamental module of this structure consists of nine semiconductor switches (eight unidirectional and one bidirectional) and four asymmetrical configured DC sources (ratio of 1:2), which can generate 13-level output voltage. To validate the design, a Matlab-Simulink based model is developed. For this paper, a Sinusoidal Pulse Width Modulation (SPWM) is deployed as the switching strategy of the proposed MLI. The circuit model is simulated under pure resistive and inductive loads. It will be shown that the circuit performs well under both loads. Comparison with traditional MLIs and other recently introduced MLIs will be conducted to show the superiority of the proposed MLI in terms of reduced number of devices and lower voltage stress across the switches.

scholarly journals Three-Phase Symmetric Cascading Z-Source Seven Levels Multilevel Inverter Excited by Multi Carrier Sinusoidal Pulse Width Modulation Scheme

2019 ◽  
Vol 8 (10) ◽  
pp. 4269-4274
Keyword(s):  
Pulse Width ◽  
Output Voltage ◽  
Pulse Width Modulation ◽  
Multilevel Inverter ◽  
Modulation Scheme ◽  
Performance Parameters ◽  
Output Waveform ◽  
Three Phase ◽  
Sinusoidal Pulse Width Modulation ◽  
Z Sources

The Multilevel Z sources Inverter have been documented as attractive topologies used for elevated voltage adaptation. As the digit of levels improved, the synthesized set of steps output waveform have many ladder, imminent the preferred sine waveform but the major weakness of MLI be its amplitude of ac output voltage is imperfect to DC input sources voltage summing up. To conquer this drawback seven level cascading symmetric multilevel inverter based Z source inverter have been projected. This work focuses on different multi-carrier sinusoidal PWM scheme for the seven level three phase Z source symmetric cascading inverter. Performance parameters of seven level three phase Z source symmetric cascading inverter has been analyzed. A simulation circuit model of seven level three phase Z source symmetric cascading inverter urbanized using MATLAB/SIMULINK and its presentation have been urbanized.

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