Power consumption reduction of an electric shower using a PWM based power supply

Author(s):  
Cindy Madrid Chirinos ◽  
Vicky Lorena Velásquez ◽  
Humberto Amador Soto
2009 ◽  
Vol E92-C (3) ◽  
pp. 352-355
Author(s):  
Ki-Sang JUNG ◽  
Kang-Jik KIM ◽  
Young-Eun KIM ◽  
Jin-Gyun CHUNG ◽  
Ki-Hyun PYUN ◽  
...  

2013 ◽  
Vol 2013 ◽  
pp. 1-11
Author(s):  
A. K. Pandey ◽  
R. A. Mishra ◽  
R. K. Nagaria

We proposed footless domino logic buffer circuit. It minimizes redundant switching at the dynamic and the output nodes. The proposed circuit avoids propagation of precharge pulse to the output node and allows the dynamic node which saves power consumption. Simulation is done using 0.18 µm CMOS technology. We have calculated the power consumption, delay, and power delay product of the proposed circuit and compared the results with the existing circuits for different logic function, loading condition, clock frequency, temperature, and power supply. Our proposed circuit reduces power consumption and power delay product as compared to the existing circuits.


2012 ◽  
Vol 229-231 ◽  
pp. 1507-1510
Author(s):  
Xiang Ning Fan ◽  
Hao Zheng ◽  
Yu Tao Sun ◽  
Xiang Yan

In this paper, a 12-bit 100MS/s pipelined ADC is designed. Capacitance flip-around structure is used in sample and hold circuit, and bootstrap structure is adopted in sampling switch which has high linearity. Progressively decreasing technology is used to reduce power consumption and circuit area, where 2.5bit/stage structure is used in the first two stages, 1.5bit/stage structure is used for 3rd to 8th stages, and at the end of the circuit is a 2bit-flash ADC. Digital calibration is designed to eliminate the offset of comparators. Switched-capacitor dynamic comparator structure is used to further reduce the power consumption. The ADC is implemented by using TSMC 0.18m CMOS process with die area be 1.23mm×2.3mm. SNDR and SFDR are 65dB and 71.3dB, when sampling at 100MHz sampling clock. The current of the circuit is 96mA under 1.8V power supply.


Author(s):  
Sheng Kang ◽  
Guofeng Chen ◽  
Chun Wang ◽  
Ruiquan Ding ◽  
Jiajun Zhang ◽  
...  

With the advent of big data and cloud computing solutions, enterprise demand for servers is increasing. There is especially high growth for Intel based x86 server platforms. Today’s datacenters are in constant pursuit of high performance/high availability computing solutions coupled with low power consumption and low heat generation and the ability to manage all of this through advanced telemetry data gathering. This paper showcases one such solution of an updated rack and server architecture that promises such improvements. The ability to manage server and data center power consumption and cooling more completely is critical in effectively managing datacenter costs and reducing the PUE in the data center. Traditional Intel based 1U and 2U form factor servers have existed in the data center for decades. These general purpose x86 server designs by the major OEM’s are, for all practical purposes, very similar in their power consumption and thermal output. Power supplies and thermal designs for server in the past have not been optimized for high efficiency. In addition, IT managers need to know more information about servers in order to optimize data center cooling and power use, an improved server/rack design needs to be built to take advantage of more efficient power supplies or PDU’s and more efficient means of cooling server compute resources than from traditional internal server fans. This is the constant pursuit of corporations looking at new ways to improving efficiency and gaining a competitive advantage. A new way to optimize power consumption and improve cooling is a complete redesign of the traditional server rack. Extracting internal server power supplies and server fans and centralizing these within the rack aims to achieve this goal. This type of design achieves an entirely new low power target by utilizing centralized, high efficiency PDU’s that power all servers within the rack. Cooling is improved by also utilizing large efficient rack based fans for airflow to all servers. Also, opening up the server design is to allow greater airflow across server components for improved cooling. This centralized power supply breaks through the traditional server power limits. Rack based PDU’s can adjust the power efficiency to a more optimum point. Combine this with the use of online + offline modes within one single power supply. Cold backup makes data center power to achieve optimal power efficiency. In addition, unifying the mechanical structure and thermal definitions within the rack solution for server cooling and PSU information allows IT to collect all server power and thermal information centrally for improved ease in analyzing and processing.


Materials ◽  
2019 ◽  
Vol 12 (17) ◽  
pp. 2758 ◽  
Author(s):  
Joseph Gonzales ◽  
Daiki Kurihara ◽  
Tetsuro Maeda ◽  
Masafumi Yamazaki ◽  
Takahito Saruhashi ◽  
...  

Ice accretion is detrimental to numerous industries, including infrastructure, power generation, and aviation applications. Currently, some of the leading de-icing technologies utilize a heating source coupled with a superhydrophobic surface. This superhydrophobic surface reduces the power consumption by the heating element. Further power consumption reduction in these systems can be achieved through an increase in passive heat generation through absorption of solar radiation. In this work, a superhydrophobic surface with increased solar radiation absorption is proposed and characterized. An existing icephobic surface based on a polytetrafluoroethylene (PTFE) microstructure was modified through the addition of graphite microparticles. The proposed surface maintains hydrophobic performance nearly identical to the original superhydrophobic coating as demonstrated by contact and roll-off angles within 2.5% of the original. The proposed graphite coating also has an absorptivity coefficient under exposure to solar radiation 35% greater than typical PTFE-based coatings. The proposed coating was subsequently tested in an icing wind tunnel, and showed an 8.5% and 50% decrease in melting time for rime and glaze ice conditions, respectively.


1997 ◽  
Vol 07 (01) ◽  
pp. 17-30 ◽  
Author(s):  
An-Chang Deng

Power consumption is a primary concern for today's IC designers. However, determining an IC's power consumption is a difficult task, as consumption varies according to input stimulus conditions. This paper will focus on (1) the principal phenomena involved in the power consumption of CMOS circuits, (2) a brief survey of power estimation techniques, and (3) the effect of power-supply noise on circuit performance plus possible solutions to this problem.


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