The fringing electric field effect on the short-channel effect threshold voltage of FD SOI NMOS devices with LDD/sidewall oxide spacer structure

Author(s):  
J.B. Kuo ◽  
Shih-Chia Lin
Author(s):  
Yuk L. Tsang ◽  
Xiang D. Wang ◽  
Reyhan Ricklefs ◽  
Jason Goertz

Abstract In this paper, we report a transistor model that has successfully led to the identification of a non visual defect. This model was based on detailed electrical characterization of a MOS NFET exhibiting a threshold voltage (Vt) of just about 40mv lower than normal. This small Vt delta was based on standard graphical extrapolation method in the usual linear Id-Vg plots. We observed, using a semilog plot, two slopes in the Id-Vg curves with Vt delta magnified significantly in the subthreshold region. The two slopes were attributed to two transistors in parallel with different Vts. We further found that one of the parallel transistors had short channel effect due to a punch-through mechanism. It was proposed and ultimately confirmed the cause was due to a dopant defect using scanning capacitance microscopy (SCM) technique.


1999 ◽  
Vol 568 ◽  
Author(s):  
M.E. Rubin ◽  
S. Saha ◽  
J. Lutze ◽  
F. Nouri ◽  
G. Scott ◽  
...  

ABSTRACTExperiment shows that the reverse short channel effect (RSCE) in nMOS devices is critically impacted by the inclusion of nitrogen in the gate oxide. A higher concentration of nitrogen results in a lessened RSCE, i.e. more threshold voltage rolloff for smaller gate lengths. We propose that the additional nitrogen reduces the interstitial recombination rate at the interface, resulting in a smaller interstitial flux and therefore less transient enhanced diffusion (TED) of boron to that interface. To test this hypothesis, we simulate boron redistribution in one and two dimensional MOS capacitor structures, as well as full nMOS devices. We then present simulations calibrated to a 0.2 pim technology currently in production.


Author(s):  
Baharak Mehrdel ◽  
Azlan Abdul Aziz ◽  
Mahdiar Hossein Ghadiri

<p><em>In this paper we present four simple analytical threshold voltage model for short- channel and length of saturation velocity region (LVSR) effect that takes into account the built – in potential of the source and drain channel junction, the surface potential and the surface electric field effect on double – gate graphene nanoribbon transistors. Four established models for surface potential, lateral electric field, LVSR and threshold voltage are presented. These models are based on the easy analytical solution of the two dimensional potential distribution in the graphene and Poisson equation which can be used to obtain surface potential, lateral electric field, LVSR and threshold voltage. These models give a closed form solution of the surface potential and electrical field distribution as a function of structural parameters and drain bias. Most of analytical outcomes are shown to correlate with outcomes acquired by Matlab simulation and the end model applicability to the published silicon base devices is demonstrated.</em></p>


1997 ◽  
Vol 490 ◽  
Author(s):  
Julie Y. H. Lee ◽  
Tom C. H. Lee ◽  
Mike Embry ◽  
Keenan Evans ◽  
Dan Koch ◽  
...  

ABSTRACTThis study calculates the threshold voltage (VT) roll-off behavior caused by short channel effect (SCE) as a result of scaling and the reverse short-channel effect (RSCE) due to B segregation around source and drain junctions by using the 2D device simulator - SILVACO™-ATLAS. The simulation results are comparable with the experimental data. It suggests that the drift diffusion physics can predict SCE and RSCE very well to sub-0.25μ Si n-MOSFET devices. The modeling results indicate the VT roll off at shorter channel length for devices with higher substrate doping concentration. VT increases if the local p-dopant segregation exists around the source and drain junction. It is observed that RSCE is more significant for devices with lower substrate doping concentration and shorter channel length.


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