LOMI: Logic Gate Multiplexer Integrated Circuit using Verilog HDL

2021 ◽  
Author(s):  
Rosemarie V. Pellegrino ◽  
Jocelyn F. Villaverde ◽  
Mark Mackoy M. Dela Pena ◽  
Liam Christopher L. Domingo
Keyword(s):  
Integrated Circuit ◽  
Logic Gate ◽  
Verilog Hdl

scholarly journals An area efficient memory-less ROM design architecture for direct digital frequency synthesizer

2021 ◽  
Vol 11 (1) ◽  
pp. 257
Author(s):  
Salah Alkurwy ◽  
Sawal H. Ali ◽  
Md. Shabiul Islam ◽  
Faizul Idros
Keyword(s):  
Frequency Synthesizer ◽  
Logic Gate ◽  
Lookup Table ◽  
Verilog Hdl ◽  
Digital Frequency ◽  
Novel Approach ◽  
Direct Digital Frequency Synthesizer ◽  
A New Technique ◽  
Simple Logic ◽  
Efficient Memory

This paper introduces a new technique of designing a read-only memory (ROM) circuit, namely; memory-less ROM as a novel approach to designing the ROM lookup table (LUT) circuit for use in a direct digital frequency synthesizer (DDFS). The proposed DDFS design uses the pipelined phase accumulator (PA) based on the kogge-stone (KS) adder. Verilog HDL programming is encoded on the architecture circuit of pipelined PA and contrasted with other PA based on various adders. The obtained results define the KS adder as having good capabilities for improving the throughput. In addition to the quarter symmetry technique, the built memory-less ROM to obtain the quarter sine amplitude waveform is proposed and implemented in the DDFS system. The implementation of the proposed technique replaces the necessary ROM registers (384 D flip-flops) and multiplexers with simple logic gate circuits instead of traditional ROMs. This technique would reduce the area size and cell count by 56% and 32.6% respectively.

Logic Gate Integrated Circuit Identification Through Augmented Reality and a Smartphone

2019 ◽  
pp. 73-85
Author(s):  
Carlos Aviles-Cruz ◽  
Juan Villegas-Cortez ◽  
Arturo Zuniga-Lopez ◽  
Ismael Osuna-Galan ◽  
Yolanda Perez-Pimentel ◽  
...  
Keyword(s):  
Augmented Reality ◽  
Integrated Circuit ◽  
Logic Gate

scholarly journals 213 AB-X integrated circuit T cells demonstrate improved potency, expansion, and specificity compared to MSLN CAR T cells

2021 ◽  
Vol 9 (Suppl 3) ◽  
pp. A226-A226
Author(s):  
Stephen Santoro ◽  
Aaron Cooper ◽  
Natalie Bezman ◽  
Jun Feng ◽  
Kanika Chawla ◽  
...  
Keyword(s):  
Ovarian Cancer ◽  
T Cells ◽  
T Cell ◽  
Integrated Circuit ◽  
Logic Gate ◽  
Xenograft Model ◽  
Car T Cells ◽  
Car T

BackgroundIn solid tumors, CAR T cell efficacy is limited by off-tumor toxicity and suppression by the tumor microenvironment (TME). AB-X is an integrated circuit T cell (ICT cell) intended for the treatment of ovarian cancer. AB-X includes a transgene cassette with two functional modules: 1) an ”AND” logic gate designed to limit off-tumor toxicity through dual tumor antigen recognition; 2) a dual shRNA-miR to resist TME suppression and improve ICT cell function. The AB-X logic gate consists of a priming receptor that induces expression of an anti-mesothelin (MSLN) CAR upon engagement of a ALPG/P (alkaline phosphatase germ-line/placental). The dual shRNA-miR mediates downregulation of FAS and PTPN2. The AB-X DNA cassette is inserted into the T cell genome at a defined novel genomic site via CRISPR-based gene editing.MethodsDual-antigen specificity of the logic gate was assessed in mice harboring MSLN+ and ALPG/P+MSLN+ K562 tumors established on contralateral flanks. Potency was measured in a subcutaneous MSTO xenograft model. Logic-gated ICT cells were compared with MSLN CAR T cells in both models. In vitro, expansion of ICT cells with the FAS/PTPN2 shRNA-miR was evaluated in a 14 day repetitive stimulation assay (RSA). In vivo, expansion and potency were measured in the MSTO xenograft model. An in vitro FAS cross-linking assay was conducted to assess the impact of FAS knockdown on FAS-mediated apoptosis.ResultsLogic-gated ICT cells demonstrated specific activity against ALPG/P+MSLN+ tumors, but had no effect against MSLN+ tumors in the K562 in vivo specificity model. In addition, logic-gated ICT cells demonstrated greater in vivo potency than MSLN CAR T cells in the MSTO xenograft model. In our RSA, ICT cells containing the FAS/PTPN2 shRNA-miR had 8-fold greater expansion than the MSLN CAR T cells. Enhanced expansion was confirmed in vivo with ICT cells demonstrating >10-fold expansion in tumors and peripheral blood, enabling comparable growth inhibition in MSTO xenografts at less than one quarter the dose of the MSLN CAR T cells. Importantly, PTPN2 knockdown resulted in balanced expansion of all T cell subsets, including CD45RA+, CCR7+ memory cells. Lastly, ICT cells containing the FAS/PTPN2 shRNA-miR were resistant to FAS-mediated apoptosis.ConclusionsAB-X ICT cells specifically recognize ALPG/P+MSLN+ tumors, demonstrate superior potency, expansion, and persistence compared with MSLN CAR T cells, and are resistant to ovarian TME suppression. AB-X will be evaluated in clinical trials for treatment of platinum resistant/refractory ovarian cancer.AcknowledgementsWe would like to acknowledge all of our colleagues at Arsenal Biosciences, without whom this work would not have been possible.

scholarly journals Logic Synthesis for Emerging Technologies

2021 ◽  
Vol 16 (1) ◽  
pp. 1-9
Author(s):  
Augusto Neutzling ◽  
Renato Perez Ribas
Keyword(s):  
Integrated Circuit ◽  
New Technologies ◽  
Emerging Technologies ◽  
Logic Gate ◽  
Logic Synthesis ◽  
Design Flow ◽  
Synthesis Process ◽  
Synthesis Methods ◽  
Threshold Logic ◽  
Mos Transistor

Emerging technologies are being considered to replace the conventional CMOS-based design that seems arriving to its end of life due to the limits of MOS transistor shrinking. However, since those novel devices are not necessarily switch-based ones, the traditional AND/OR logic synthesis process in the digital integrated circuit design flow tends to become inefficient, whereas threshold logic paradigm seems to be more appropriate for them. In this context, different methods for threshold logic synthesis, suitable for emerging technologies, are reviewed in this paper. The majority logic based design is also discussed herein since it represents a subset of threshold logic domain, and many new technologies have presented the 3-input majority Boolean function as the most basic logic gate. Experimental data, presented in previous works, are used to illustrate and compare the performance of the state-ofthe-art       logic synthesis methods related to

Very Large Scale Integrated-Circuit Architecture for Offset Quadrature Phase Shift Keying Modulation Using Offset Generator

2019 ◽  
Vol 17 (11) ◽  
pp. 884-887
Author(s):  
Alphyn Stanley ◽  
R.K. Sharma
Keyword(s):  
Phase Shift ◽  
Integrated Circuit ◽  
Large Scale ◽  
Combinational Logic ◽  
Phase Shift Keying ◽  
Verilog Hdl ◽  
Maximum Phase ◽  
Quadrature Phase Shift Keying ◽  
Quadrature Phase ◽  
Shift Keying

This work presents an architecture for Offset Quadrature Phase Shift Keying (OQPSK) using an Offset generator. The Offset generator generates symbol patterns such that there is a maximum phase shift of ±90° only between the symbols, unlike the Quadrature Phase Shift Keying (QPSK) modulator which has a maximum of ±180° phase shift. Here the effort of designing an Offset generator, which can be embedded onto QPSK modulator to generate OQPSK with minimum combinational logic, has been discussed. Whenever the input symbols to the Offset generator varies in phase with a ±180° in constellation, it generates an intermediate symbol which differs only in ±90° with the previous one. Then it continues to give out the original symbol to be transmitted. This follows the exact OQPSK technology while it doesn't follow the conventional generation method of OQPSK modulation which provides an offset between the even and odd bit patterns of the symbols to be transmitted. The architecture is modelled using Verilog HDL and the functionality is validated from the simulation result.

scholarly journals GERBANG LOGIKA BERBASIS PROGRAMMABLE LOGIC DEVICE (PLD)

2009 ◽  
Vol 1 (1) ◽  
pp. 75-81
Author(s):  
Muhammad Irmansyah
Keyword(s):  
Integrated Circuit ◽  
High Speed ◽  
Logic Gate ◽  
Data Communication ◽  
Programmable Logic ◽  
Single Chip ◽  
Logic Device ◽  
Logic Devices ◽  
Programmable Logic Device ◽  
Programmable Logic Devices

In middle 1990, electronics industry had evolution in personal Computer, telephone cellular and high speed data communication equipment. To follow this development, electronics companies have designed and produce new product. One of these innovations is Programmable Logic Devices (PLD) technology. It is a technology to change function of IC digital logic using programming. Many of Programmable Logic Device (PLD) can be used to programming logic using single chip of integrated circuit (IC). Programmable Logic Devices (PLD) technology is applied using IC PAL 22V10 to design basic logic gate AND, OR, NOT and combinational logic gate NAND and NOR.

New device for automatic recording and processing AV transmission intervals of the heart

1976 ◽  
Vol 41 (5) ◽  
pp. 784-789
Author(s):  
S. Akiyama ◽  
T. Oshima ◽  
Y. Saito ◽  
K. Matsuda
Keyword(s):  
Experimental Animal ◽  
Integrated Circuit ◽  
Logic Gate ◽  
Automatic Recording ◽  
Atrioventricular Conduction ◽  
New Device ◽  
Refractory Periods ◽  
Mode Of Operation ◽  
On Line ◽  
Coupling Time

The principle and construction of a device made for the purpose of displaying the interrelationship between two sets of cardiac intervals is described. Electrical signals derived from the atrium and ventricle of the experimental animal are fed to the input of the device where a special switch andan integrated circuit logic gate select the two sets of cardiac intervals to be measured, e.g., AA and VV or AA and AV intervals. These intervals are converted into electrical square pulses having voltages proportional to therespective intervals. Besides simply comparing the two cardiac intervals byrecording them simultaneously against time, the interrelationship of the two is displayed in an X-Y configuration on-line on a cathode-ray oscilloscope. This latter method, if used only for the occasionally induced premature excitations with varied coupling time, facilitates the measurement of the functional refractory periods for atrioventricular conduction. The mode of operation of the device is presented with examples of experiments.

The ASIC Design and Verification Based on Verilog HDL

2012 ◽  
Vol 433-440 ◽  
pp. 4578-4583
Author(s):  
Yu Ying Yuan ◽  
Yong Gang Luo
Keyword(s):  
Design Process ◽  
Integrated Circuit ◽  
Logic Design ◽  
Verilog Hdl ◽  
Asic Design ◽  
Application Specific Integrated Circuit ◽  
Design Requirements ◽  
Cross Connect ◽  
Application Specific ◽  
Important Design

Logic design and verification is the frontend of ASIC (Application Specific Integrated Circuit), and is a very important design part during the design process of ASIC. A Verilog HDL design case－2×2 SDH digital cross-connect matrix is provided to illustrate the entire design process including logic-level description, verification and synthesis based on the frontend tools of Synopsys. After that a gate-level netlist conforming to the design requirements can be obtained.

The Design and Implement of a Receiver for FSK Signal

2012 ◽  
Vol 190-191 ◽  
pp. 739-741
Author(s):  
Xiao Peng Liu ◽  
Yan Han ◽  
Dong Dong Zhong ◽  
Ming Yu Wang
Keyword(s):  
Integrated Circuit ◽  
Low Noise ◽  
Matlab Simulation ◽  
Verilog Hdl ◽  
Cmos Integrated Circuit ◽  
Bit Error Ratio ◽  
Shift Keying ◽  
Field Programmable ◽  
Band Pass ◽  
Noise Amplifier

A novel frequency shift keying (FSK) receiver is presented, including receiving antennas, a low noise amplifier (LNA), band-pass filters (BPF) and a novel all-digital 2-level FSK demodulator. The Matlab simulation results of the all-digital FSK demodulator show that it can improve bit error ratio (BER) performance compared with pseudo-coherent FSK demodulation (PCFSK). The novel FSK demodulator defined using Verilog HDL is easy to be implemented on Field Programmable Gate Array (FPGA) and in CMOS integrated circuit. The whole FSK receiver designed and implemented on a PCB board can receive FSK signal and send the recovered data to computer through RS-232 interface.

scholarly journals Secure Fault Diagnosis for Framework on Chip Design and Testing

2020 ◽  
Vol 9 (5) ◽  
pp. 715-720
Keyword(s):  
Fault Diagnosis ◽  
Circuit Design ◽  
Integrated Circuit ◽  
Research Paper ◽  
Verilog Hdl ◽  
Integrated Circuit Design ◽  
Chip Design ◽  
Cell Plan ◽  
On Chip ◽  
Design And Testing

Because of the extensive expense of semiconductor fabricating, most framework on-chip structure organizations redistribute their generation to seaward foundries. As a large portion of these gadgets are fabricated in situations of constrained trust that regularly need suitable oversight, various diverse dangers have risen. These incorporate unapproved overabundance of the ICs, offer of out-of-determination/rejected ICs disposed of by assembling tests, robbery of scholarly property, and figuring out of the structures. The Boolean calculations are effectively break keybased confusion techniques and therefore go around the essential destinations of metering and confusion. In this research paper, we present an innovation secure cell plan for executing the structure for-security foundation to avoid releasing the way to a foe under any conditions and produce fault free integrated circuit design. Our proposed structure is impervious to different known assaults at the expense of a next to no region overhead. This Proposed Framework Actualized utilizing Verilog HDL also recreated by Modelsim 6.4 c and Integrated by Xilinx device.

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