Thermo-Viscoelastic Analysis of Deflection in CSP Electronic Device Packages

2003 ◽  
Vol 125 (3) ◽  
pp. 414-419 ◽  
Author(s):  
Hideo Koguchi ◽  
Chie Sasaki ◽  
Kazuto Nishida
Keyword(s):  
Integrated Circuit ◽  
Electronic Device ◽  
Plate Theory ◽  
Bonding Temperature ◽  
Temperature History ◽  
Viscoelastic Analysis ◽  
Chip Scale Package ◽  
Multilayered Plates ◽  
Bonding Technology ◽  
Method Analysis

In the present paper, a deformation induced in a new bonding technology of chip-scale package (CSP) using resin encapsulation sheets is examined numerically and experimentally. Deflections after cooling from a bonding temperature are measured experimentally for various kinds of substrate and the thickness of an integrated circuit using a laser beam. In particular, a simple theory on the basis of a multilayered plate theory considering a viscoelastic property in the substrate is presented, and the thermo-viscoelastic analysis for the deflection of CSP is performed. Furthermore, the thermo-elastoplastic finite element method analysis is performed under the same temperature history. We could show that the simple formula for multilayered plates based on the thermo-viscoelatic theory can estimate fairly well the deflection of CSP in experiment.

Low Temperature flip chip bonding technology applicable to flexible hybrid electronics in the IoT era

2019 ◽  
Vol 2019 (DPC) ◽  
pp. 000474-000518
Author(s):  
Hiroshi Komatsu
Keyword(s):  
Screen Printing ◽  
Flip Chip ◽  
Bonding Temperature ◽  
Complex Form ◽  
Fine Tuning ◽  
Electric Resistance ◽  
Flip Chip Bonding ◽  
Strong Adhesion ◽  
Bonding Technology ◽  
Ag Paste

Since its early days of the industry, electronics apparatus has been in a rigid and flat surfaced case. ICs have been soldered on rigid substrate at high bonding temperature. However, in the IoT era, electronics components connect with the variety of applications which require different forms and shapes of outlook which lead substrate and board should be flexible and complex form. Conventional flip chip bonding technology, such as solder bump and copper pillar, need to raise bonding temperature around 260-degree C, eventually does not satisfy this flexile hybrid electronics (FHE) application requirement. We have originally developed flip chip bonding technology which consists of the bump formation by Conductive Paste (CP) printing followed by Non-Conductive Paste (NCP) dispensing and flip chip bonding at temperature as low as 120-degree C. Bumps with silver particle loaded epoxy resin on substrate were formed by screen printing. This enable us to make fine bump formation down to 60um minimum bump pitch and 30um bump diameter with tuning of screen-printing process. After the bump formation, NCP dispensing and flip chip bonding at 120-degree C which secure reasonable low electric resistance, 8×1E-4 ohm cm2, and strong adhesion of chip and substrate. The bonding temperature of this technology can be lowered down to 80-degree C without much difficulties, but just by fine tuning of Ag paste and its contents. This momentum will create a lot more of future applications and be one of the core technologies in the coming IoT era in FHE.

Temporary and Permanent Adhesives for Thin Wafer Handling and Assembly

2013 ◽  
Vol 2013 (DPC) ◽  
pp. 001009-001032
Author(s):  
Mark Oliver ◽  
Jong-Uk Kim ◽  
Michael Gallagher ◽  
Zidong Wang ◽  
Janet Okada ◽  
...  
Keyword(s):  
Wafer Bonding ◽  
Spin Coating ◽  
Bonding Temperature ◽  
High Volume ◽  
Wafer Surface ◽  
Process Time ◽  
Adhesion Promoter ◽  
Excellent Thermal Stability ◽  
Carrier Wafer ◽  
Bonding Technology

Temporary wafer bonding has emerged as the method of choice for handling silicon wafers during the thinning and high-temperature backside processing required for the manufacture of 3D device structures. Among the requirements for temporary wafer bonding materials to be used in high volume manufacturing are simple device and carrier wafer preparation, high-throughput wafer bonding, excellent thermal stability, and clean room-temperature release directly from the device wafer. We will present successful temporary wafer bonding using a new BCB (benzocyclobutene)-based material that can meet these requirements. For this temporary wafer bonding technology, wafer preparation involves spin coating the device wafer with the BCB-based adhesive to a thickness of up to 100 μm and spin coating the carrier wafer with an adhesion promoter. The wafers can then be bonded at temperatures as low as 80 °C for as short as 30 seconds. The low bonding temperature means the wafers can be loaded into a preheated wafer bonding tool, eliminating the time needed to heat and cool the bonding chucks during the bonding cycle. Also, no curing of the material is required during the bonding, enabling a short process time and high wafer throughput. Curing of the adhesive is done as a batch oven cure at 210 °C for one hour after which the material is stable enough for backside processes up to 300 °C. The material has been designed to adhere well to the carrier wafer and debond directly from the device wafer without any chemical or radiation pretreatment, leaving a clean device wafer surface in need of only mild cleaning before further processing.

A process analysis for microchannel deformation and bonding strength by in-mold bonding of microfluidic chips

2015 ◽  
Vol 35 (3) ◽  
pp. 267-275 ◽  
Author(s):  
Chunpeng Chu ◽  
Bingyan Jiang ◽  
Laiyu Zhu ◽  
Fengze Jiang
Keyword(s):  
Bonding Strength ◽  
Process Analysis ◽  
Bonding Temperature ◽  
Bonding Time ◽  
Production Cycle ◽  
Microfluidic Chips ◽  
Bonding Pressure ◽  
Bonding Parameters ◽  
Bonding Technology ◽  
Assembly Technology

Abstract A novel combination of thermal bonding and in-mold assembly technology was created to produce microfluidic chips out of polymethylmethacrylate (PMMA), which is named “in-mold bonding technology”. In-mold bonding experiments of microfluidic chips were carried out to investigate the influences of bonding process parameters on the deformation and bonding strength of microchannels. The results show that bonding temperature has the greatest impact on the deformation of microchannels, while bonding pressure and bonding time have more influence on deformation in height than in top width. Considering the bonding strength, the bonding temperature and the bonding pressure have more impact than the bonding time. The time is crucial for the sealing of the chips. By setting the bonding parameters reasonably, the microchannel deformation is <10%, while the bonding strength of the chips is 350 kPa. The production cycle of the chip is reduced to <5 min.

Research on Bonding of PMMA Microfluidic Chip with Precisely Controlled Bonding Pressure

2011 ◽  
Vol 221 ◽  
pp. 8-14 ◽  
Author(s):  
Bing Yan Jiang ◽  
Zhou Zhou ◽  
Yao Liu
Keyword(s):  
Microfluidic Chip ◽  
Simulation Analysis ◽  
Bonding Temperature ◽  
Production Cycle ◽  
Microfluidic Chips ◽  
Bonding Pressure ◽  
Finite Element Software ◽  
Conventional Procedure ◽  
Bonding Technology ◽  
Increasing Temperature

Microfluidic chips have a great prospect in the field of biochemical analysis with advantages of fast processes, high flux and low consumption. Molding and bonding are separated by the conventional procedure of hot embossing and bonding, resulting in low automation and long production cycle. In order to reduce cycle time and achieve mass production, this paper proposed In-mold Bonding technology with precisely controlled bonding pressure by injection molding machine’s movement of core-pulling. So simulation analysis for bonding process of PMMA microfluidic chip was carried out using finite element software to study microchannel distortion at different bonding temperature and pressure. The results show that, at a certain bonding pressure, when bonding temperature was lower than glass transition temperature(Tg), microchannel distortion didn’t change significantly, when bonding temperature was higher than Tg, microchannel deformation increases with increasing temperature. Small microchannel distortion was obtained at a temperature of 108°C,which was recommended as the suitable bonding temperature.

The Engineering of Silicon Wafer Material Properties Through Vacancy Concentration Profile Control and the Achievement of Ideal Oxygen Precipitation Behavior

1998 ◽  
Vol 510 ◽  
Author(s):  
R. Falster ◽  
D. Gambaro ◽  
M. Olmo ◽  
M. Cornara ◽  
H. Korb
Keyword(s):  
Silicon Wafer ◽  
Integrated Circuit ◽  
Defect Formation ◽  
Electronic Device ◽  
Vacancy Concentration ◽  
Silicon Wafers ◽  
Precipitation Behavior ◽  
Oxygen Precipitation ◽  
Profile Control ◽  
Zone Depth

AbstractA new kind of silicon wafer and a new class of materials engineering techniques for silicon wafers is described. This wafer, called the “Magic Denuded Zone” or MDZ wafer, is produced through the manipulation of the vacancy concentration and, in particular, vacancy concentration depth profiles in the wafer prior to the development of oxygen precipitates in subsequent heat treatments. The result is a wafer with ideal oxygen precipitation behavior for use in all types of integrated circuit applications. The methods used to prepare such wafers combine Frenkel pair generation with injection and the use of surface sinks. Simulations of the vacancy profiles produced by these techniques are presented and discussed. It is shown that within the range of vacancy concentration accessible by these techniques (up to ca. 1013 cm−3) the rate and oxygen concentration dependence of oxygen clustering can be substantially modified. Such techniques can be used to precisely engineer unique and desirable oxygen-related defect performance in silicon wafers both in terms of distribution and rate of defect formation. One result of the application of such techniques is an ideally precipitating silicon wafer in which the resulting oxygen precipitate profile (denuded zone depth and bulk density of precipitates) is independent of the concentration of oxygen of the wafer, the details of the crystal growth process used to prepare the wafer and, to a very large extent, the details of thermal cycles used to process the wafer into an electronic device. Optimal, generic and reliable internal gettering performance is achieved in such a wafer

Low Temperature Cu–Cu Bonding Technology in Three-Dimensional Integration: An Extensive Review

2018 ◽  
Vol 140 (1) ◽  
Author(s):  
Asisa Kumar Panigrahy ◽  
Kuan-Neng Chen
Keyword(s):  
Low Temperature ◽  
Integrated Circuit ◽  
Large Scale ◽  
Three Dimensional ◽  
3D Ic ◽  
Bonding Technology ◽  
Three Dimensional Integrated Circuit ◽  
Low Temperature Bonding ◽  
Cu Bonding

Arguably, the integrated circuit (IC) industry has received robust scientific and technological attention due to the ultra-small and extremely fast transistors since past four decades that consents to Moore's law. The introduction of new interconnect materials as well as innovative architectures has aided for large-scale miniaturization of devices, but their contributions were limited. Thus, the focus has shifted toward the development of new integration approaches that reduce the interconnect delays which has been achieved successfully by three-dimensional integrated circuit (3D IC). At this juncture, semiconductor industries utilize Cu–Cu bonding as a key technique for 3D IC integration. This review paper focuses on the key role of low temperature Cu–Cu bonding, renaissance of the low temperature bonding, and current research trends to achieve low temperature Cu–Cu bonding for 3D IC and heterogeneous integration applications.

Efficient Diffusion Bonding between BSCCO Superconducting Multifilamentary Tapes

2008 ◽  
Vol 580-582 ◽  
pp. 295-298
Author(s):  
Gui Sheng Zou ◽  
Yan Ju Wang ◽  
Ai Ping Wu ◽  
Hai Lin Bai ◽  
Nai Jun Hu ◽  
...  
Keyword(s):  
High Temperature ◽  
Diffusion Bonding ◽  
New Technology ◽  
Bonding Temperature ◽  
Interface Bonding ◽  
Bonding Pressure ◽  
Bonding Parameters ◽  
Efficient Diffusion ◽  
Bonding Technology ◽  
Multifilamentary Tapes

To improve the joining efficiency of Bi-Sr-Ca-Cu-O ( BSCCO) superconducting tapes, a new diffusion bonding technology with a direct uniaxial pressing at high temperature was developed to join 61-filament tapes. It was observed that bonding parameters such as bonding pressure and holding time, significantly affected the critical current ratio (CCRo). A peak CCRo value of 89 % for the lap-joined tapes was achieved at 3 MPa for 2 h when bonding temperature was 800 °C. Compared with the conventional diffusion bonding technology, this new technology remarkably shortened the fabrication period and improved the superconductivity of the joints. The bonding interface and microstructures of the joints were evaluated and correlated to the CCRo. An uniaxial pressing at high temperature was beneficial to interface bonding, and there was an optimal pressure value for the CCRo.

An Overview of Integrated Circuit Device Encapsulants

1989 ◽  
Vol 111 (2) ◽  
pp. 97-107 ◽  
Author(s):  
C. P. Wong
Keyword(s):  
Integrated Circuit ◽  
Large Scale ◽  
Electronic Device ◽  
Rapid Development ◽  
Polymer Materials ◽  
Organic Polymer ◽  
Small Scale ◽  
Steady Increase ◽  
Chip Size ◽  
Scale Integration

The rapid development of integrated circuit technology from small-scale integration (SSI) to very large scale integration (VLSI) has had great technological and economical impact on the electronics industry. The exponential growth of the number of components per IC chip, the exponential decrease of device dimensions, and the steady increase in IC chip size have imposed stringent requirements, not only on the IC physical design and fabrication, but also on IC encapsulants. This report addresses the purpose of encapsulation, encapsulation techniques, and a general overview of the application of inorganic and organic polymer materials as electronic device encapsulants.

High Density Direct Bond Interconnect (DBI) Technology for Three Dimensional Integrated Circuit Applications

2006 ◽  
Vol 970 ◽  
Author(s):  
Paul Enquist
Keyword(s):  
Wafer Bonding ◽  
Integrated Circuit ◽  
Three Dimensional ◽  
High Density ◽  
Temperature Cycling ◽  
Direct Wafer Bonding ◽  
Part Yield ◽  
Bond Interface ◽  
Bonding Technology ◽  
Three Dimensional Integrated Circuit

ABSTRACTA novel direct wafer bonding technology capable of forming a very high density of electrical interconnections across the bond interface integral to the bond process is described. Results presented include an 8 um interconnection pitch, die-to-wafer and wafer-to-wafer bonding formats, temperature cycling reliability × 10 greater than the JEDEC requirement, connection yield ∼ 99.999, > 50% part yield on parts with ∼ 450,000 connections, and < 0.1 Ohm connection resistance at 1pA without requiring a voltage surge to induce current.

Sign in / Sign up

Export Citation Format

Share Document