A Review of Recent Advances in Thermal Management in Three Dimensional Chip Stacks in Electronic Systems

2011 ◽  
Vol 133 (4) ◽  
Author(s):  
Vikram Venkatadri ◽  
Bahgat Sammakia ◽  
Krishnaswami Srihari ◽  
Daryl Santos
Keyword(s):  
Thermal Analysis ◽  
Integrated Circuits ◽  
Thermal Management ◽  
Management Strategies ◽  
Research Work ◽  
Experimental Studies ◽  
Three Dimensional ◽  
3D Integration ◽  
The Past ◽  
Planar Circuits

Three dimensional (3D) integration offers numerous electrical advantages like shorter interconnection distances between different dies in the stack, reduced signal delay, reduced interconnect power and design flexibilities. The main enabler of 3D integration is through-silicon-vias (TSVs) and stacking of multiple dies. Irrespective of these advantages, thermal management in 3D stacks poses significant challenges for the implementation of 3D integrated circuits. Even though extensive research work has been done in understanding the thermal management in two dimensional (2D) planar circuits for the past several decades, 3D integration offers a new set of challenges in terms of thermal management, which makes it difficult to readily apply the thermal management strategies available for 2D planar circuits. Over the past decade, some work has been done in thermal analysis and management of 3D stacks but still, knowledge is scattered and a comprehensive understanding is lacking. This research work focuses on bringing together the limited work on thermal analysis and thermal management in 3D vertically integrated circuits available in the literature. A compilation and analysis of the results from investigations on thermal management in 3D stacks is presented in this review with special emphasis on experimental studies conducted on different thermal management strategies. Furthermore, 3D integration technologies, thermal management challenges, and advanced 2D thermal management solutions are discussed.

Thermal Characterization of Interlayer Microfluidic Cooling of Three-Dimensional Integrated Circuits With Nonuniform Heat Flux

2010 ◽  
Vol 132 (4) ◽  
Author(s):  
Yoon Jo Kim ◽  
Yogendra K. Joshi ◽  
Andrei G. Fedorov ◽  
Young-Joon Lee ◽  
Sung-Kyu Lim
Keyword(s):  
Integrated Circuits ◽  
Mass Flow Rate ◽  
Thermal Management ◽  
Mass Flow ◽  
Flow Rate ◽  
Single Phase ◽  
Hot Spot ◽  
Three Dimensional ◽  
Two Phase ◽  
Two Phase Cooling

It is now widely recognized that the three-dimensional (3D) system integration is a key enabling technology to achieve the performance needs of future microprocessor integrated circuits (ICs). To provide modular thermal management in 3D-stacked ICs, the interlayer microfluidic cooling scheme is adopted and analyzed in this study focusing on a single cooling layer performance. The effects of cooling mode (single-phase versus phase-change) and stack/layer geometry on thermal management performance are quantitatively analyzed, and implications on the through-silicon-via scaling and electrical interconnect congestion are discussed. Also, the thermal and hydraulic performance of several two-phase refrigerants is discussed in comparison with single-phase cooling. The results show that the large internal pressure and the pumping pressure drop are significant limiting factors, along with significant mass flow rate maldistribution due to the presence of hot-spots. Nevertheless, two-phase cooling using R123 and R245ca refrigerants yields superior performance to single-phase cooling for the hot-spot fluxes approaching ∼300 W/cm2. In general, a hybrid cooling scheme with a dedicated approach to the hot-spot thermal management should greatly improve the two-phase cooling system performance and reliability by enabling a cooling-load-matched thermal design and by suppressing the mass flow rate maldistribution within the cooling layer.

Transient Thermal Analysis for the Automotive Underhood and Underbody Components

2013 ◽  
Author(s):  
Yu Hsien Wu ◽  
Kumar Srinivasan ◽  
Steven Patterson ◽  
Emmanuel Bot
Keyword(s):  
Thermal Analysis ◽  
Thermal Management ◽  
Dissimilar Materials ◽  
Thermal Mass ◽  
New Approach ◽  
The Past ◽  
Full Vehicle ◽  
Development Cycle ◽  
Transient Thermal ◽  
Steady State Solutions

The transient thermal simulation is an important part of thermal management development for new vehicle architectures. Different techniques have been studied in the past to address this coupled conduction/convection/radiation problem. In order to fully capture the transient thermal behavior of various underhood and underbody components, it is also necessary to accurately model the thermal mass of each part and the thermal links between dissimilar materials. The paper will outline a new, efficient methodology for this type of thermal analysis that shows acceptable results for complex full vehicle thermal analysis without sacrificing accuracy. The methodology is based on approximating the transient convective field with intermittent steady state solutions. The paper will present results from this new approach and compare them with fully transient simulation results as well as experimental data. The new methodology can be optimized to significantly reduce simulation run times without sacrificing accuracy and to be more practical for application in the vehicle development cycle.

Thermal Analysis of High Efficiency High Speed Drives

2019 ◽  
Author(s):  
Yasmin Khakpour ◽  
Weilun Warren Chen ◽  
Parikshith Channegowda ◽  
Matthew R. Pearson ◽  
Yongduk Lee ◽  
...  
Keyword(s):  
Thermal Analysis ◽  
Thermal Resistance ◽  
Power Electronics ◽  
Thermal Management ◽  
High Speed ◽  
High Efficiency ◽  
Management Strategies ◽  
Substantial Reduction ◽  
Operating Conditions ◽  
Heat Conducting

Abstract The thermal management of the PCB based power electronics is a key element to ensure safe operating conditions and to meet lifetime, reliability and safety requirements. This is challenging for applications above 1 kW because the substrate material used in a PCB such as FR-4 has very low heat conducting properties. Hence, there is a limit on how much loss can be dissipated from the board and for that reason this approach has only been adopted in the industry for very low power applications. With the proposed multilevel topology, WBG devices, and innovative thermal management strategies it is possible to expand the PCB based power electronics approach to power ratings between 1kW and 10 kW. For instance, an improvement in the thermal resistance of the PCB can be obtained by soldering a discrete WBG device with a TO-263 package directly on a PCB with about one inch square copper area around the device which will act as a heat spreader. Then, a further substantial reduction in the thermal resistance of a PCB is possible by the application of electrical vias. In principle each via is a copper sleeve through the board or through a part of the board. Where, instead of using its electrical function, a via can also be used as a thermal conductor. In this work, the thermal analysis of the PCB and the effect of number of vias as well as the effect of filling the vias with a thermally conductive material has been studied. The design has been optimized for the number of vias and the modeling results have been verified with experimental tests.

Thermoelectric Coolers for Hotspot Thermal Management of 3D Stacked Chips

2011 ◽  
Author(s):  
Matthew Redmond ◽  
Kavin Manickaraj ◽  
Owen Sullivan ◽  
Satish Kumar
Keyword(s):  
Integrated Circuits ◽  
Thermal Management ◽  
Power Density ◽  
Hot Spot ◽  
Thermal Contact ◽  
Three Dimensional ◽  
Heat Removal ◽  
Thermoelectric Coolers ◽  
Vertical Coupling ◽  
Spot Cooling

Three dimensional (3D) technologies with stacked chips have the potential to provide new chip architecture, improved device density, performance, efficiency, and bandwidth. Their increased power density also can become a daunting challenge for heat removal. Furthermore, power density can be highly non-uniform leading to time and space varying hotspots which can severely affect performance and reliability of the integrated circuits. Thus, it is important to mitigate thermal gradients on chip while considering the associated cooling costs. One method of thermal management currently under investigation is the use of superlattice thermoelectric coolers (TECs) which can be employed for on demand and localized cooling. In this paper, a detailed 3D thermal model of a stacked electronic package with two dies and four ultrathin integrated TECs is studied in order to investigate the efficacy of TECs in hot spot cooling for a 3D technology. We observe up to 14.6 °C of cooling at a hot spot inside the package by TECs. A strong vertical coupling has been observed between the TECs located in top and bottom dies. Bottom TECs can detrimentally heat the top hotspots in both steady state and transient operation. TECs need to be carefully placed inside the package to avoid such undesired heating. Thermal contact resistances between dies, inside the TEC module, and between the TEC and heat spreader are shown to have a crucial effect on TEC performance inside the package. We observed that square root current pulse can provide very efficient short-duration transient cooling at hotspots.

Experimental Analysis Model of an Active Cooling Method for 3D-ICs Utilizing Multidimensional Configured Thermoelectric Coolers

2010 ◽  
Vol 132 (2) ◽  
Author(s):  
Huy N. Phan ◽  
Dereje Agonafer
Keyword(s):  
Integrated Circuits ◽  
Thermal Management ◽  
Heat Dissipation ◽  
Three Dimensional ◽  
Analysis Model ◽  
Thermoelectric Coolers ◽  
Active Cooling ◽  
3D Ics ◽  
Cooling Method ◽  
Memory Applications

Presently, stack dice are used widely as low-power memory applications because thermal management of 3D architecture such as high-power processors inherits many thermal challenges. Inadequate thermal management of three-dimensional integrated circuits (3D-ICs) leads to reduction in performance, reliability, and ultimately system catastrophic failure. Heat dissipation of 3D systems is highly nonuniform and nonunidirectional due to many factors such as power architectures, transistors packing density, and real estate available on the chip. In this study, the development of an experimental model of an active cooling method to cool a 25 W stack-dice to approximately 13°C utilizing a multidimensional configured thermoelectric will be presented.

Design Guideline to Improve Thermal Management of 3D Package Using Cu-to-Cu Direct Bonding

2015 ◽  
Author(s):  
Ah-Young Park ◽  
S. B. Park
Keyword(s):  
Integrated Circuits ◽  
Thermal Management ◽  
Thermal Loading ◽  
Three Dimensional ◽  
Design Guidelines ◽  
Element Analysis ◽  
Design Guideline ◽  
Management Perspective ◽  
3D Packaging ◽  
3D Package

Three-dimensional (3D) packaging technology is directly related to the increasing I/O number as stacking chips. This technology has the potential to produce integrated circuits with a much better combination of cost, functionality, performance and power consumption. However, stacked chips raise several thermal issues that need to be addressed and eliminated. In this study, a quantitative study of the conventional solder-based interconnection is conducted based on many different cases of thermal loading, using finite element analysis (FEA). This preliminary study clearly shows limitation of the solder-based interconnection in the thermal management perspective. Underfill for microbμmp acts as a barrier of heat transfer in the conventional 3D stacked chip packages. Therefore, as an alternative, Cu-to-Cu direct bonding (CuDB), which has a better thermal conductivity, is proposed. Its parametric study is performed under the same/different loading conditions and dimensions. This study helps to highlight the thermal behavior of 3D packages consisting of various interconnections. Finally, based on the results, we can propose qualitative design guidelines of 3D packaging depending on various environment and conditions.

scholarly journals An Analysis of 3D Steganography Techniques

Electronics ◽  
2021 ◽  
Vol 10 (19) ◽  
pp. 2357
Author(s):  
Rohit Tanwar ◽  
Urmila Pilania ◽  
Mazdak Zamani ◽  
Azizah Abdul Manaf
Keyword(s):  
Image Processing ◽  
Systematic Study ◽  
Research Work ◽  
Three Dimensional ◽  
3D Images ◽  
The Past ◽  
Work Done ◽  
Evaluation Parameters

Steganography has become a preferred technique these days to successfully hide secret messages. Various research has been done in the past to justify and analyze suitable types of cover file, such as images, audio, videos, etc. Advancement in the image-processing domain has opened various possibilities of using three-dimensional (3D) images as cover files. In this paper, a systematic study of the research work done on 3D steganography in the last fifteen years has been carried out. The study is divided into different sections based on the types of algorithms used, additional security features, evaluation parameters, etc. Moreover, certain steganalysis techniques that are applicable for 3D steganography are also discussed.

scholarly journals THERMAL MODEL FOR ELECTROMAGNETIC LAUNCHERS

2008 ◽  
Vol 7 (2) ◽  
pp. 60
Author(s):  
H. Zhao ◽  
J. A. Souza ◽  
J. C. Ordonez
Keyword(s):  
Thermal Management ◽  
Body Movement ◽  
Management Strategies ◽  
Three Dimensional ◽  
Temperature Response ◽  
Heat Diffusion ◽  
Transient Temperature ◽  
Three Dimensional Model ◽  
Electromagnetic Launchers ◽  
Electromagnetic Launcher

This paper presents a 3D model for the determination of the temperature field in an electromagnetic launcher. The large amounts of energy that are dissipated into the structure of an electromagnetic launcher during short periods of time lead to a complicated thermal management situation. Effective thermal management strategies are necessary in order to maintain temperatures under acceptable limits. This paper constitutes an attempt to determine the temperature response of the launcher. A complete three-dimensional model has been developed. It combines rigid body movement, electromagnetic effects and heat diffusion together. The launcher consists of two parallel rectangular rails and an armature moving between them. Preliminary results show the current distribution on the rail cross-section, the localized resistive heating, and the rail transient temperature response. The simulation results are compared to prior work presented for a 2D geometry by Powell and Zielinski (2008).

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