Reliable Design of TSV in Free-Standing Wafers and 3D Integrated Packages

2011 ◽  
Author(s):  
Xi Liu ◽  
Margaret Simmons-Matthews ◽  
Kurt P. Wachtler ◽  
Suresh K. Sitaraman
Keyword(s):  
Integrated Circuit ◽  
Mechanical Performance ◽  
Semiconductor Industry ◽  
Three Dimensional ◽  
Wafer Level ◽  
Free Standing ◽  
Design Factor ◽  
Reliable Design ◽  
Reliability Issue ◽  
Key Enabling Technologies

Through-silicon via (TSV), being one of the key enabling technologies for three dimensional (3D) Integrated Circuit (IC) stacking, silicon interposer technology, and advanced wafer level packaging (WLP), has attracted tremendous interest throughout the semiconductor industry. However, limited work addresses TSV reliability issue, and most of the existing reliability studies focus on the thermo-mechanical performance of TSVs in a free-standing wafer, rather than in an integrated package. In this paper, three-dimensional thermomechanical Finite-Element (FE) models with TSVs in both free-standing wafers and 3D integrated packages have been built and analyzed. In addition, Design of Experiments (DOE) based approach has been used to understand the effect of various parameters. Results show that the selection of underfill materials between stacked dies is the most dominating design factor for TSV/microbump reliability.

Reliable Design of Electroplated Copper Through Silicon Vias

2010 ◽  
Author(s):  
Xi Liu ◽  
Qiao Chen ◽  
Venkatesh Sundaram ◽  
Sriram Muthukumar ◽  
Rao R. Tummala ◽  
...  
Keyword(s):  
System Integration ◽  
Coefficient Of Thermal Expansion ◽  
Three Dimensional ◽  
Interfacial Stress ◽  
Through Silicon Vias ◽  
Fabrication Defects ◽  
Reliable Design ◽  
Electroplated Copper ◽  
Key Enabling Technologies ◽  
Silicon Vias

Through-silicon vias (TSVs), being one of the key enabling technologies for 3D system integration, are being used in various 3D vertically stacked devices. As TSVs are relatively new, there is not enough information in available literature on the thermo-mechanical reliability of TSVs. Due to the high coefficient of thermal expansion (CTE) mismatch between Si and the Cu vias, “Cu pumping” will occur at high temperature and “Cu sinking” will occur at low temperature, which may induce large stress in SiO2, interfacial stress at Cu/SiO2 interface and plastic deformation in Cu core. The thermal-mechanical stress can potentially cause interfacial debonding, cohesive cracking in dielectric layers or Cu core, causing some reliability issues. Thus, in this paper, three-dimensional thermo-mechanical finite-element models have been built to analyze the stress/strain distribution in the TSV structures. A comparative analysis of different via designs, such as circular, square, and annular vias has been performed. In addition, defects due to fabrication such as voids in the Cu core during electroplating and Cu pad undercutting due to over-etching are considered in the models, and it is seen that these fabrication defects are detrimental to TSV reliability.

scholarly journals Reliability and Performance of Wafer Level Fan Out Package for Automotive Radar

2021 ◽  
Vol 34 (1) ◽  
pp. 32-39
Author(s):  
Walter Hartner ◽  
Martin Niessner ◽  
Francesca Arcioni ◽  
Markus Fink ◽  
Christian Geissler ◽  
...  
Keyword(s):  
Phase Shift ◽  
Thermal Performance ◽  
Integrated Circuit ◽  
Solder Ball ◽  
Mechanical Performance ◽  
Special Focus ◽  
Wafer Level ◽  
Automotive Radar ◽  
Thermal Measurements ◽  
The Impact

Embedded wafer level ball grid array (eWLB) or FO-WLP (Fan-out wafer-level packaging) is investigated as a package for MMICs (Monolithic Microwave Integrated Circuit) for automotive radar applications in the 77GHz range. Special focus is put on the thermo-mechanical performance to achieve automotive quality targets. The typical fatigue modes “solder ball fatigue” and “copper fatigue”, evolving during thermo-mechanical stress like cycling on board will be discussed. Simulation as well as experimental preparation results for typical fatigue levels are given. In addition, several influencing parameters are listed and rated regarding their effectiveness. The theoretical framework why solder ball fatigue is the only failure mode causing electrical failure is provided.   The impact of different thermo-mechanically driven fatigue modes is discussed. The two important parameters to be considered for the functionality of the Radar system are RF (Radio Frequency) and thermal performance.   For elaborating the RF performance with present fatigue modes, the phase shift between different channels and pads is analyzed by full-wave EM (Electromagnetic) simulation. It is found that for fatigue levels up to 90% the phase shift stays below specification for single fatigue modes and may approach specification only for an unlikely combination of all 90% fatigue modes.   For assessing the thermal performance with present fatigue modes, thermal simulation as well as thermal measurements are used. Assuming 50% degradation in average for all thermal balls, an increase in RTH of up to about 30% is seen. On average for all thermal measurements, the deviation between measurement and simulation is within ±1°C.

Non-Destructive 3D Failure Analysis Work Flow for Electrical Failure Analysis in Complex 2.5D-Based Devices Combining 3D Magnetic Field Imaging and 3D X-Ray Microscopy

2018 ◽  
Author(s):  
Antonio Orozco ◽  
Elena Talanova ◽  
Alex Jeffers ◽  
Florencia Rusli ◽  
Bernice Zee ◽  
...  
Keyword(s):  
Magnetic Field ◽  
Failure Analysis ◽  
Integrated Circuit ◽  
Semiconductor Industry ◽  
Three Dimensional ◽  
X Ray ◽  
Electrical Failure ◽  
Magnetic Field Imaging ◽  
3D Stacking ◽  
Field Imaging

Abstract Industry and market requirements keep imposing demands in terms of tighter transistor packing, die and component real estate management on the package, faster connections and expanding functionality. This has forced the semiconductor industry to look for novel packaging approaches to allow for 3D stacking of transistors (the so called “More than Moore”). This complex 3D geometry, with an abundance of opaque layers and interconnects, presents a great challenge for failure analysis (FA). Three-dimensional (3D) magnetic field imaging (MFI) has proven to be a natural, useful technique for non-destructively mapping 3D current paths in devices that allows for submicron vertical resolution. 3D X-ray microscopy (XRM) enables 3D tomographic imaging of advanced IC packages without the need to destroy the device. This is because it employs both geometric and optical image magnifications to achieve high spatial resolution. In this paper, we propose a fully nondestructive, 3D-capable workflow for FA comprising 3D MFI and 3D XRM. We present an application of this novel workflow to 3D defect localization in a complex 2.5D device combining high bandwidth memory (HBM) devices and an application specific integrated circuit (ASIC) unit on a Si interposer with a signal pin electrical short failure.

Dielectric GlueWafer Bonding For 3D ICs

2003 ◽  
Vol 766 ◽  
Author(s):  
Y. Kwon ◽  
A. Jinda ◽  
J.J. McMahon ◽  
J.Q. Lu ◽  
R.J. Gutmann ◽  
...  
Keyword(s):  
Integrated Circuit ◽  
Bonding Strength ◽  
Three Dimensional ◽  
Wafer Level ◽  
Four Point Bending ◽  
Mechanical And Electrical Properties ◽  
3D Ics ◽  
Bond Interface ◽  
Three Dimensional Integrated Circuit ◽  
Wafer Thinning

AbstractA process to bond 200 mm wafers for wafer-level three-dimensional integrated circuit (3D-IC) applications is discussed. Four-point bending is used to quantify the bonding strength and identify the weak interface. Using benzocylcobutene (BCB) glue, the bonding strength depends on (1) glue thickness, (2) glue film preparation, and (3) materials and structures on the wafer(s). A seamless BCB-to-BCB bond interface provides the highest bonding strength compared to other interfaces in these structures (> 34 J/m2). Mechanical and electrical properties of a wafer with copper interconnect structures are preserved after wafer bonding and wafer thinning, confirming the potential of the bonding process for 3D ICs.

scholarly journals A Solder Based Self Assembly Project In An Introductory IC Fabrication Course

2015 ◽  
Vol 6 (1) ◽  
pp. 11-26 ◽  
Author(s):  
Madhav Rao ◽  
John C Lusth ◽  
Susan L Burkett
Keyword(s):  
Integrated Circuit ◽  
Self Assembly ◽  
Semiconductor Industry ◽  
Three Dimensional ◽  
Cost Effective ◽  
Deposition Process ◽  
Design Stage ◽  
Laboratory Course ◽  
Final Project ◽  
Hands On

Integrated circuit (IC) fabrication principles is an elective course in a senior undergraduate and early graduate student’s curriculum. Over the years, the semiconductor industry relies heavily on students with developed expertise in the area of fabrication techniques, learned in an IC fabrication theory and laboratory course. The theory course gives importance to the physics of manufacturing techniques and is often attached to a subsequent semester laboratory curriculum. The pre-requisite requirement of the theory component for a laboratory course requires students to enroll for two courses in separate semesters and is not an option for all students. Hence, an innovative student project is intended in the theory curriculum to give hands-on experience on the processes. The IC fabrication course is usually associated with high enrollment of students, leading to fewer laboratory experiments. The physics of IC fabrication techniques is important, but few students may perceive the theory as important with no laboratory experience. To improve the course and give students hands-on practice with existing state-of-the-art processing facilities, a tailored project was added to the syllabus. A solder-based self assembly (SBSA) project was introduced in the curriculum for the first time at the University of Alabama in Fall 2011. The student projects were designed in a way to provide an alternative to conventional time-intensive, high cost, and highly tool dependent IC fabrication lab experiments. SBSA forms three dimensional (3D) structures when applied to two dimensional (2D) patterns. The schedule was designed to accommodate theory classes aligned with the fabrication steps and completed by students. The project involved a brainstorming session, a design stage to develop 2D patterns using AutoCAD software, a deposition process, a lithography step, a dip soldering step, a reflow process, scanning electron microscope (SEM) imaging, and a final project presentation. Other processes required to complete the project were performed by the instructor. In general, students showed interest in working in teams, completing the project, and recommended to continuing the SBSA project in future IC fabrication course work. The SBSA project is cost effective and less tool dependent for incorporation in a semester long course. In addition, the project is time effective from both student and instructor perspectives. 

Global Planarization Requirements for Wafer-Level Three-Dimensional (3D) ICs

2005 ◽  
Author(s):  
R. J. Gutmann ◽  
J. J. McMahon ◽  
J.-Q. Lu
Keyword(s):  
Integrated Circuit ◽  
Thermal Processing ◽  
Three Dimensional ◽  
Wafer Level ◽  
3D Integration ◽  
3D Ics ◽  
Technology Platforms ◽  
Technology Focus ◽  
Feature Scale ◽  
Ic Technology

Planarization needs for integrated circuit (IC) technology focus on feature-scale (100nm–1μm) and die-scale (5mm-20mm) dimensions. As three-dimensional (3D) integration moves from die-by-die assembly to wafer-level integration to provide a higher density of low electrical parasitic vertical interconnects (or vias), wafer-level planarization needs to be considered. Planarization needs depend upon the 3D technology platform approach (such as (1) blanket bonding followed by inter-wafer interconnect processing or via-first processing followed by bonding and thinning to expose the vias and (2) the number of wafers in a 3D stack) and the processing conditions used in fabricating the wafers to be 3D integrated (in particular, the built-in stress levels and post-bonding thermal processing budget). This invited presentation includes a summary of the current interest in wafer-level 3D integration in both the academic and industrial research community. Wafer-level planarization issues with different technology platforms are presented, and the limited results presented in the literature to date are summarized. The importance of wafer-level planarization compared to bonding, thinning and wafer-to-wafer alignment is discussed.

Enhancement of through Silicon via Sidewall Quality by Nanosecond Laser Pulses with Chemical Etching Process

2012 ◽  
Vol 579 ◽  
pp. 3-9 ◽  
Author(s):  
Chao Wei Tang ◽  
Shih Chieh Tseng ◽  
Hong Tsu Young ◽  
Kuan Ming Li ◽  
Mike Yang ◽  
...  
Keyword(s):  
Integrated Circuit ◽  
Chemical Etching ◽  
Three Dimensional ◽  
Laser Pulses ◽  
Nanosecond Laser ◽  
Wafer Level ◽  
Sidewall Roughness ◽  
Through Silicon Via ◽  
Three Dimensional Integrated Circuit ◽  
Micrometer Scale

Through-silicon via (TSV) is an emerging technology for three-dimensional integrated circuit, system in package, and wafer level packaging applications. In this study, a wet chemical etching (WCE) process has been employed to enhance the sidewall quality of TSVs fabricated using nanosecond (ns) laser pulses. Experimental results show that the TSV sidewall roughness can be markedly reduced, from micrometer scale to nanometer scale. We concluded that the proposed method would enable semiconductor manufactures to use ns laser drilling for industrial TSV fabrication as the desired TSV sidewall quality can be achieved by incorporating the WCE process, which is suitable for mass production.

Scanning Electron Microscopy in Hybrid Microelectronics

1976 ◽  
Vol 34 ◽  
pp. 456-457
Author(s):  
S. Khadpe ◽  
R. Faryniak
Keyword(s):  
Integrated Circuits ◽  
Thick Film ◽  
Integrated Circuit ◽  
Failure Modes ◽  
Three Dimensional ◽  
Circuit Components ◽  
Hybrid Microcircuit ◽  
Electrical Connections ◽  
Scanning Electron

The Scanning Electron Microscope (SEM) is an important tool in Thick Film Hybrid Microcircuits Manufacturing because of its large depth of focus and three dimensional capability. This paper discusses some of the important areas in which the SEM is used to monitor process control and component failure modes during the various stages of manufacture of a typical hybrid microcircuit.Figure 1 shows a thick film hybrid microcircuit used in a Motorola Paging Receiver. The circuit consists of thick film resistors and conductors screened and fired on a ceramic (aluminum oxide) substrate. Two integrated circuit dice are bonded to the conductors by means of conductive epoxy and electrical connections from each integrated circuit to the substrate are made by ultrasonically bonding 1 mil aluminum wires from the die pads to appropriate conductor pads on the substrate. In addition to the integrated circuits and the resistors, the circuit includes seven chip capacitors soldered onto the substrate. Some of the important considerations involved in the selection and reliability aspects of the hybrid circuit components are: (a) the quality of the substrate; (b) the surface structure of the thick film conductors; (c) the metallization characteristics of the integrated circuit; and (d) the quality of the wire bond interconnections.

Analyzing the Impact of X-Ray Tomography on the Reliability of Integrated Circuits

2015 ◽  
Author(s):  
Halit Dogan ◽  
Md Mahbub Alam ◽  
Navid Asadizanjani ◽  
Sina Shahbazmohamadi ◽  
Domenic Forte ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
3D Imaging ◽  
Three Dimensional ◽  
Serial Sectioning ◽  
Promising Technique ◽  
Flash Memories ◽  
X Ray ◽  
3D Information ◽  
The Impact

Abstract X-ray tomography is a promising technique that can provide micron level, internal structure, and three dimensional (3D) information of an integrated circuit (IC) component without the need for serial sectioning or decapsulation. This is especially useful for counterfeit IC detection as demonstrated by recent work. Although the components remain physically intact during tomography, the effect of radiation on the electrical functionality is not yet fully investigated. In this paper we analyze the impact of X-ray tomography on the reliability of ICs with different fabrication technologies. We perform a 3D imaging using an advanced X-ray machine on Intel flash memories, Macronix flash memories, Xilinx Spartan 3 and Spartan 6 FPGAs. Electrical functionalities are then tested in a systematic procedure after each round of tomography to estimate the impact of X-ray on Flash erase time, read margin, and program operation, and the frequencies of ring oscillators in the FPGAs. A major finding is that erase times for flash memories of older technology are significantly degraded when exposed to tomography, eventually resulting in failure. However, the flash and Xilinx FPGAs of newer technologies seem less sensitive to tomography, as only minor degradations are observed. Further, we did not identify permanent failures for any chips in the time needed to perform tomography for counterfeit detection (approximately 2 hours).

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