Mechanical Design Optimization of a Package on Package

2009 ◽  
Author(s):  
Abhilash R. Menon ◽  
Nikhil Lakhkar ◽  
Saket Karajgikar ◽  
Dereje Agonafer
Keyword(s):  
High Performance ◽  
Heat Dissipation ◽  
Mechanical Design ◽  
Three Dimensional ◽  
Die Attach ◽  
Optimization Function ◽  
Solder Joint Fatigue ◽  
Number Of Cycles ◽  
Packaging Structure ◽  
Silicon Vias

In the past decade, compact components such as Chip Scale Packages and flip chips were the work horses of miniaturization. However, emerging applications are now demanding even higher packaging density. In order to fulfill this requirement, three dimensional packaging was evolved. Advantages of three dimensional packaging structure include minimal conductor length and eliminate speed limiting inter chip interconnects. In order to reduce signal delays and to increase heat dissipation, lot of solutions like through silicon vias, thermal vias, stacking were implemented. Stacked packages are finding applications ranging from high-end servers to mobility products. Most common applications of stacked packages include high performance memory, DRAM, logic-memory stack, system in a package etc. Stacked packages can be package-on-package or die stacked (with several dice inside the same casing) or both. The thermo-mechanical design of package on package is very complex and often requires elaborate models and analysis with considerable CPU time. In this paper we have considered a package with both die stacking and package on package. In the first part of this study we considered a variety of cases resembling the applications that stacked CSP can go into. In this study, we have considered various geometries to optimize the design mechanically in thermo-cycling loading. The optimization function for this study is to minimize the package height without compromising its reliability in terms of thermo-cycles. “Package on package” family of packages is expensive to operate and to fabricate hence a prior simulation of various geometry of interconnects is necessary to understand how the package is going to behave in terms of number of cycles. In this study we have considered different thicknesses of die, die attach, top substrate and bottom substrate to optimize solder joint fatigue life. In this study SAC405 is considered.

Numerical Analysis for Thermal Performance of High Power Multi-Chip LED Packaging

2010 ◽  
Vol 139-141 ◽  
pp. 1433-1437
Author(s):  
Kai Lin Pan ◽  
Jiao Pin Wang ◽  
Jing Liu ◽  
Guo Tao Ren
Keyword(s):  
High Power ◽  
Heat Sink ◽  
Heat Dissipation ◽  
Light Emitting Diode ◽  
Three Dimensional ◽  
Junction Temperature ◽  
Light Emitting ◽  
Die Attach ◽  
Dissipation Model ◽  
Key Issues

Heat dissipation and cost are the key issues for light-emitting diode (LED) packaging. In this paper, based on the thermal resistance network model of LED packaging, three-dimensional heat dissipation model of high power multi-chip LED packaging is developed and analyzed with the application of finite element method. Temperature distributions of the current multi-chip LED packaging model are investigated systematically under the different materials of the chip substrate, die attach, and/or different structures of the heat sink and fin. The results show that the junction temperature can be decreased effectively by increasing the height of the heat sink, the width of the fin, and the thermal conductivity of the chip substrate and die attach materials. The lower cost and higher reliability for LED source can be obtained through reasonable selection of materials and structure parameters of the LED lighting system.

Compact Transient Thermal Model of Microfluidically Cooled Three-Dimensional Stacked Chips With Pin-Fin Enhanced Microgap

2021 ◽  
Vol 143 (3) ◽  
Author(s):  
Yuanchen Hu ◽  
Md Obaidul Hossen ◽  
Zhimin Wan ◽  
Muhannad S. Bakir ◽  
Yogendra Joshi
Keyword(s):  
Heat Transfer ◽  
Integrated Circuit ◽  
High Performance ◽  
Heat Dissipation ◽  
Three Dimensional ◽  
Heat Removal ◽  
Power Estimation ◽  
Leakage Power ◽  
Pin Fin ◽  
Pin Fins

Abstract Three-dimensional (3D) stacked integrated circuit (SIC) chips are one of the most promising technologies to achieve compact, high-performance, and energy-efficient architectures. However, they face a heat dissipation bottleneck due to the increased volumetric heat generation and reduced surface area. Previous work demonstrated that pin-fin enhanced microgap cooling, which provides fluidic cooling between layers could potentially address the heat dissipation challenge. In this paper, a compact multitier pin-fin single-phase liquid cooling model has been established for both steady-state and transient conditions. The model considers heat transfer between layers via pin-fins, as well as the convective heat removal in each tier. Spatially and temporally varying heat flux distribution, or power map, in each tier can be modeled. The cooling fluid can have different pumping power and directions for each tier. The model predictions are compared with detailed simulations using computational fluid dynamics/heat transfer (CFD/HT). The compact model is found to run 120–600 times faster than the CFD/HT model, while providing acceptable accuracy. Actual leakage power estimation is performed in this codesign model, which is an important contribution for codesign of 3D-SICs. For the simulated cases, temperatures could decrease 3% when leakage power estimation is adopted. This model could be used as electrical-thermal codesign tool to optimize thermal management and reduce leakage power.

A Micro-channel Cooling Model For a Three-dimensional Integrated Circuit Considering Through-silicon Vias

2020 ◽  
Vol 12 ◽  
Author(s):  
Kang-Jia Wang ◽  
Hong-Chang Sun ◽  
Kui-Zhi Wang
Keyword(s):  
Integrated Circuit ◽  
Heat Dissipation ◽  
Three Dimensional ◽  
Micro Channel ◽  
3D Ic ◽  
Through Silicon Vias ◽  
3D Ics ◽  
Three Dimensional Integrated Circuit ◽  
Silicon Vias ◽  
Cooling Model

Background: With the increase of the integration degree of the three-dimensional integrated circuit(3D IC), the thermal power consumption per unit volume increases greatly, which makes the chip temperature rise. High temperature could affect the performance of the devices and even lead to thermal failure. So, the thermal management for 3D ICs is becoming a major concern. Objective: The aim of the research is to establish a micro-channel cooling model for a three-dimensional integrated circuit(3D IC) considering the through-silicon vias(TSVs). Methods: By studying the structure of the TSVs, the equivalent thermal resistance of each layer is formulated. Then the one-dimensional micro-channel cooling thermal analytical model considering the TSVs was proposed and solved by the existing sparse solvers such as KLU. Results: The results obtained in this paper reveal that the TSVs can effectively improve the heat dissipation, and its maximal temperature reduction is about 10.75%. The theoretical analysis is helpful to optimize the micro-channel cooling system for 3D ICs. Conclusion: The TSV has an important influence on the heat dissipation of 3D IC, which can improve its heat dissipation characteristic

Electrical Interconnect and Microfluidic Cooling Within 3D ICs and Silicon Interposer

2014 ◽  
Author(s):  
Hanju Oh ◽  
Yue Zhang ◽  
Li Zheng ◽  
Muhannad S. Bakir
Keyword(s):  
Integrated Circuits ◽  
Thermal Gradient ◽  
Heat Dissipation ◽  
Three Dimensional ◽  
Heat Removal ◽  
3D Ic ◽  
Significant Challenge ◽  
3D Ics ◽  
Silicon Vias ◽  
First Time

Heat dissipation is a significant challenge for three-dimensional integrated circuits (3D IC) due to the lack of heat removal paths and increased power density. In this paper, a 3D IC system with an embedded microfluidic cooling heat sink (MFHS) is presented. In the proposed 3D IC system, high power tiers contain embedded MFHS and high-aspect ratio (23:1) through-silicon-vias (TSVs) routed through the integrated MFHS. In addition, each tier has dedicated solder-based microfluidic chip I/Os. Microfluidic cooling experiments of staggered micropin-fins with embedded TSVs are presented for the first time. Moreover, the lateral thermal gradient across a chip is analyzed with segmented heaters.

scholarly journals High-Performance Temporary Adhesives for Wafer Bonding Applications

2006 ◽  
Vol 970 ◽  
Author(s):  
Rama Puligadda ◽  
Sunil Pillalamarri ◽  
Wenbin Hong ◽  
Chad Brubaker ◽  
Markus Wimplinger ◽  
...  
Keyword(s):  
High Performance ◽  
Heat Dissipation ◽  
Driving Forces ◽  
Three Dimensional ◽  
Temperature Stability ◽  
Thickness Variation ◽  
High Temperature Stability ◽  
Process Step ◽  
Wide Range ◽  
Wafer Thinning

ABSTRACTMyriad structures for stacking chips, power devices, smart cards, and thin substrates for processors have one thing in common: thin silicon. Wafer thinning will soon be an essential process step for most of the devices fabricated and packaged henceforth. The key driving forces for thinned wafers are improved heat dissipation, three-dimensional stacking, reduced electrical resistance, and substrate flexibility. Handling of thin and ultrathin substrates however is not trivial because of their fragility and tendency to warp and fold. The thinned substrates need to be supported during the backside grinding process and through the subsequent processes such as lithography, deposition, etc. Using temporary adhesives to attach the processed device wafer to a rigid carrier wafer offers an efficient solution. The key requirements for such materials are ease of application, coating uniformity with minimal thickness variation across the wafer, good adhesion to a wide variety of surfaces, thermal stability in processes such as dielectric deposition and metallization, and ease of removal to allow high throughput. An additional requirement for these materials is stability in harsh chemical environments posed by processes such as etching and electroplating. Currently available materials meet only a subset of these requirements. None of them meet the requirement of high-temperature stability combined with ease of removal. We have developed adhesives that meet a wide range of post-thinning operating temperatures. Additionally, the materials are soluble in industry-accepted safe solvents and can be spin-applied to required thicknesses and uniformity. Above all, the coatings can be removed easily without leaving any residue. This paper reports on the development of a wide range of temporary adhesives that can be used in wafer thinning applications while applying both novel and conventional bonding and debonding methods.

Through Silicon Vias (TSVs) Technology for MEMS Packaging

2010 ◽  
Vol 154-155 ◽  
pp. 1695-1698 ◽  
Author(s):  
Kai Lin Pan ◽  
Jing Liu ◽  
Jiao Pin Wang ◽  
Jing Huang
Keyword(s):  
High Performance ◽  
Three Dimensional ◽  
Test Method ◽  
Wafer Level ◽  
Through Silicon Vias ◽  
Mems Packaging ◽  
Wafer Level Packaging ◽  
Critical Issues ◽  
Silicon Vias ◽  
Two Sides

Through silicon vias (TSVs) provide advanced vertical interconnections solutions for system-in-package (SiP) (such as chip to chip, chip to wafer, and wafer to wafer stacking), wafer-level packaging, interposer packaging. At present the shortest electrical path (vertical electrical feed through) between two sides of a silicon chip is one of the important applications. In order to achieve high density and high performance package, TSVs technology has been developed. And for three-dimensional (3D) MEMS (Microelectromechanical System) packaging, TSVs are the most important enabling technology. In this paper, some advantages of TSVs technology are described, and process flow of TSVs module is introduced firstly. Subsequently, a novel electricity test method of Non-Ideal Planes for TSVs is introduced. Finally, many critical issues and challenges of TSVs are reviewed.

Solder Based Self-Assembled Structures for 3D Integration

2014 ◽  
Vol 875-877 ◽  
pp. 1604-1609
Author(s):  
Madhav Rao
Keyword(s):  
Integrated Circuit ◽  
Heat Dissipation ◽  
Three Dimensional ◽  
3D Structures ◽  
Solder Bumps ◽  
Additional Processing ◽  
Measured Resistance ◽  
Self Assembled ◽  
Silicon Vias ◽  
3D Chip Stacking

A novel way of three dimensional (3D) chip stacking has been designed in a view to improve heat dissipation across the layers. Chip stacking using vertical interconnections forms microscale channels for coolant to circulate through the gaps. Solder-based self-assembled (SBSA) 3D structures have been designed as posts on simulated through silicon vias (TSVs) to prove the processing concept. The processing of SBSA structures using a low temperature solder alloy and dip soldering method is described. Additional processing steps to fabricate interconnected 3D structures were demonstrated. Mechanical grinding of the 3D structures shows that soldered SBSA structures were void free and robust enough to be used as a connection post for chip stacking. SBSA structures provide a solder bump that serves as a connection path in the integration of dissimilar electronic technologies. Conventional copper posts, developed in a previous project, can be an effective approach to integrated circuit (IC) stacking. However, the SBSA post provides more variety in size and shape with a potential to serve as a reservoir for solder to aid in chip bonding. The solder bumps are heat resistant and uniform thicknesses were obtained across a large array of SBSA structures. The electrical durability of SBSA posts were determined by completing I-V measurements after thermal treatments. Fabricated SBSA posts were subjected to thermal cycling with temperatures ranging from room temperature to 300 °C. The interconnected SBSA posts are shown to be stable until 165 °C with little variation in measured resistance.

Benchmarking Study on the Thermal Management Landscape for Three-Dimensional Integrated Circuits: From Back-Side to Volumetric Heat Removal

2016 ◽  
Vol 138 (1) ◽  
Author(s):  
Thomas Brunschwiler ◽  
Arvind Sridhar ◽  
Chin Lee Ong ◽  
Gerd Schlottig
Keyword(s):  
Integrated Circuits ◽  
Thermal Management ◽  
Integrated Circuit ◽  
Power Dissipation ◽  
High Performance ◽  
Heat Dissipation ◽  
Hybrid Approach ◽  
Three Dimensional ◽  
Heat Removal ◽  
Back Side

An overview of the thermal management landscape with focus on heat dissipation from three-dimensional (3D) chip stacks is provided in this study. Evolutionary and revolutionary topologies, such as single-side, dual-side, and finally, volumetric heat removal, are benchmarked with respect to a high-performance three-tier chip stack with an aggregate power dissipation of 672 W. The thermal budget of 50 K can be maintained by three topologies, namely: (1) dual-side cooling, implemented by a thermally active interposer, (2) interlayer cooling with four-port fluid delivery and drainage at 100 kPa pressure drop, and (3) a hybrid approach combining interlayer with embedded back-side cooling. Of all the heat-removal concepts, interlayer cooling is the only approach that scales with the number of dies in the chip stack and hence enables extreme 3D integration. However, the required size of the microchannels competes with the requirement of low through-silicon-via (TSV) heights and pitches. A scaling study was performed to derive the TSV pitch that is compatible with cooling channels to dissipate 150 W/cm2 per tier. An active integrated circuit (IC) area of 4 cm2 was considered, which had to be implemented on the varying tier count in the stack. A cuboid form factor of 2 mm × 4 mm × 2.55 mm results from a die count of 50. The resulting microchannels of 2 mm length allow small hydraulic diameters and thus a very high TSV density of 1837 1/mm2. The accumulated heat flux and the volumetric power dissipation are as high as 7.5 kW/cm2 and 29 kW/cm3, respectively.

A High Performance Full SiC Power Module Based On a Novel Stacked DBCs Hybrid Packaging Structure

2019 ◽  
Vol 2019 (1) ◽  
pp. 000557-000562
Author(s):  
Zhiwei Wang ◽  
Chi Zhang ◽  
Zhizhao Huang ◽  
Cai Chen ◽  
Fang Luo
Keyword(s):  
High Performance ◽  
Layer Structure ◽  
Three Dimensional ◽  
Dynamic Test ◽  
Test Results ◽  
Switching Loss ◽  
Power Module ◽  
Pulse Testing ◽  
Power Testing ◽  
Packaging Structure

Abstract This paper proposed a novel stacked DBCs hybrid package structure and designed a low inductive 1200V/120A SiC half-bridge power module based on the package structure. Using the multi-layer structure of DBC+DBC, the main loop parasitic inductance of the power module has been reduced to 1.8nH by optimizing the three-dimensional commutation loop and using the mutual inductance cancellation concept. The module was designed and fabricated, the low inductance characteristics of the module was verified by dual pulse testing and power testing. Dynamic test results show that the module can switch safely with a low overvoltage under zero ohm external drive resistance, and the switching loss is reduced by 57% compared to commercial modules.

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