Benchmarking Study on the Thermal Management Landscape for Three-Dimensional Integrated Circuits: From Back-Side to Volumetric Heat Removal

2016 ◽  
Vol 138 (1) ◽  
Author(s):  
Thomas Brunschwiler ◽  
Arvind Sridhar ◽  
Chin Lee Ong ◽  
Gerd Schlottig
Keyword(s):  
Integrated Circuits ◽  
Thermal Management ◽  
Integrated Circuit ◽  
Power Dissipation ◽  
High Performance ◽  
Heat Dissipation ◽  
Hybrid Approach ◽  
Three Dimensional ◽  
Heat Removal ◽  
Back Side

An overview of the thermal management landscape with focus on heat dissipation from three-dimensional (3D) chip stacks is provided in this study. Evolutionary and revolutionary topologies, such as single-side, dual-side, and finally, volumetric heat removal, are benchmarked with respect to a high-performance three-tier chip stack with an aggregate power dissipation of 672 W. The thermal budget of 50 K can be maintained by three topologies, namely: (1) dual-side cooling, implemented by a thermally active interposer, (2) interlayer cooling with four-port fluid delivery and drainage at 100 kPa pressure drop, and (3) a hybrid approach combining interlayer with embedded back-side cooling. Of all the heat-removal concepts, interlayer cooling is the only approach that scales with the number of dies in the chip stack and hence enables extreme 3D integration. However, the required size of the microchannels competes with the requirement of low through-silicon-via (TSV) heights and pitches. A scaling study was performed to derive the TSV pitch that is compatible with cooling channels to dissipate 150 W/cm2 per tier. An active integrated circuit (IC) area of 4 cm2 was considered, which had to be implemented on the varying tier count in the stack. A cuboid form factor of 2 mm × 4 mm × 2.55 mm results from a die count of 50. The resulting microchannels of 2 mm length allow small hydraulic diameters and thus a very high TSV density of 1837 1/mm2. The accumulated heat flux and the volumetric power dissipation are as high as 7.5 kW/cm2 and 29 kW/cm3, respectively.

Benchmarking Study on the Thermal Management Landscape for 3D ICs: From Back-Side to Volumetric Heat Removal

2015 ◽  
Author(s):  
Thomas Brunschwiler ◽  
Arvind Sridhar ◽  
Chin Lee Ong ◽  
Gerd Schlottig
Keyword(s):  
Thermal Management ◽  
Power Dissipation ◽  
High Performance ◽  
Heat Dissipation ◽  
Hybrid Approach ◽  
Heat Removal ◽  
Back Side ◽  
Cooling Channels ◽  
Fluid Delivery ◽  
Single Side

An overview of the thermal management landscape with focus on heat dissipation from 3D chip stacks is provided in this study. Evolutionary and revolutionary topologies, such as single-side, dual-side and, finally, volumetric heat removal, are benchmarked with respect to a high-performance three-tier chip stack with an aggregate power dissipation of 672 W. The thermal budget of 50 K can be maintained by three topologies, namely, 1) dual-side cooling, implemented by a thermally active interposer, 2) interlayer cooling with 4-port fluid delivery and drainage at 100 kPa pressure drop, and 3) a hybrid approach combining interlayer with embedded back-side cooling. Of all the heat-removal concepts, interlayer cooling is the only approach that scales with the number of dies in the chip stack and hence, enables extreme 3D integration. However, the required size of the microchannels competes with the requirement of low TSV heights and pitches. A scaling study was performed to derive the TSV pitch that is compatible with cooling channels to dissipate 150 W/cm2 per tier. An active IC area of 4 cm2 was considered, which had to be implemented on the varying tier count in the stack. A cuboid form factor of 2 mm × 4 mm × 2.55 mm results from a die count of 50. The resulting microchannels of 2 mm length allow small hydraulic diameters and thus a very high TSV density of 1837 1/mm2. The accumulated heat flux and the volumetric power dissipation are as high as 7.5 kW/cm2 and 29kW/cm3, respectively.

Compact Transient Thermal Model of Microfluidically Cooled Three-Dimensional Stacked Chips With Pin-Fin Enhanced Microgap

2021 ◽  
Vol 143 (3) ◽  
Author(s):  
Yuanchen Hu ◽  
Md Obaidul Hossen ◽  
Zhimin Wan ◽  
Muhannad S. Bakir ◽  
Yogendra Joshi
Keyword(s):  
Heat Transfer ◽  
Integrated Circuit ◽  
High Performance ◽  
Heat Dissipation ◽  
Three Dimensional ◽  
Heat Removal ◽  
Power Estimation ◽  
Leakage Power ◽  
Pin Fin ◽  
Pin Fins

Abstract Three-dimensional (3D) stacked integrated circuit (SIC) chips are one of the most promising technologies to achieve compact, high-performance, and energy-efficient architectures. However, they face a heat dissipation bottleneck due to the increased volumetric heat generation and reduced surface area. Previous work demonstrated that pin-fin enhanced microgap cooling, which provides fluidic cooling between layers could potentially address the heat dissipation challenge. In this paper, a compact multitier pin-fin single-phase liquid cooling model has been established for both steady-state and transient conditions. The model considers heat transfer between layers via pin-fins, as well as the convective heat removal in each tier. Spatially and temporally varying heat flux distribution, or power map, in each tier can be modeled. The cooling fluid can have different pumping power and directions for each tier. The model predictions are compared with detailed simulations using computational fluid dynamics/heat transfer (CFD/HT). The compact model is found to run 120–600 times faster than the CFD/HT model, while providing acceptable accuracy. Actual leakage power estimation is performed in this codesign model, which is an important contribution for codesign of 3D-SICs. For the simulated cases, temperatures could decrease 3% when leakage power estimation is adopted. This model could be used as electrical-thermal codesign tool to optimize thermal management and reduce leakage power.

Thermal Issues in Next Generation Integrated Circuits

2003 ◽  
Author(s):  
Siva Gurrum ◽  
Shivesh Suman ◽  
Yogendra Joshi ◽  
Andrei Fedorov
Keyword(s):  
Integrated Circuits ◽  
Thermal Management ◽  
Power Dissipation ◽  
High Performance ◽  
Electronic Devices ◽  
Heat Removal ◽  
Current Generation ◽  
Fundamental Limits ◽  
Convection Boundary ◽  
And Performance

Effective cooling of electronic chips is crucial for reliability and performance of electronic devices. Steadily increasing power dissipation in both devices and interconnects motivate the investigation of chip-centric thermal management as opposed to traditional package-centric solutions. In this work, we explore the fundamental limits for heat removal from a model chip for various configurations. Temperature rise when the chip is embedded in an infinite solid is computed for different thermal conductivities of the medium to pin down the best that can be achieved with conduction based thermal management. Next, a chip attached to a spreader plate with convection boundary condition on top was considered. A brief review of interface thermal resistances and partitioning of overall thermal resistance is presented for current generation microprocessors. Based upon the analysis it is concluded that far-term cooling solutions might necessitate integration with chip/interconnect-stack to meet the challenges. In addition, this would require concurrent thermal and electrical design/fabrication of future high-performance microprocessors.

Ceramic-Based Planar Heat Pipe (Plate) for Passive Electronics Cooling

2011 ◽  
Vol 2011 (CICMT) ◽  
pp. 000159-000165
Author(s):  
M. Wilson ◽  
H. Anderson ◽  
J. Fellows ◽  
C. Lewinsohn
Keyword(s):  
Integrated Circuits ◽  
Phase Change ◽  
Heat Dissipation ◽  
Thermal Contact ◽  
Three Dimensional ◽  
Electronics Cooling ◽  
Ceramic Materials ◽  
Back Side ◽  
Dimensional Network ◽  
Internal Networks

Heat dissipation has become a major hurdle for the electronics industry, especially as higher performance integrated circuits are being developed for the power industry. Two of the primary hurdles in dissipating this heat are:The thermal contact resistance between the IC and the cooling device.The ability to effectively spread the heat, such that traditional cooling technologies can be effective.By selecting ceramic materials that are thermo-mechanically matched (CTE) to IC materials, the proposed heat plate can be directly bonded by typical solder or braze techniques to the back-side of the IC. This eliminates thermal resistances due to contact and thermal interface materials. Within these heat plates, a three dimensional network of gas channels and fluid wicks spread the high-flux heat loads from localized hot spots to the surrounding regions via phase change fluids and mass transport. Like traditional heat pipes, these heat plates operate at nearly uniform temperature due to the phase change. The internal networks provide for multidimensional heat and mass flow, increasing their dissipating capability. By using matched ceramic materials, and the inclusion of a heat plate, these primary hurdles for heat dissipation can be mitigated. The performance of prototypical planar heat plates will be presented.

Layout Based Full Chip Thermal Simulations of Stacked 3D Integrated Circuits

2003 ◽  
Author(s):  
Ashok Raman ◽  
Marek Turowski ◽  
Monte Mar
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
Hot Spots ◽  
Heat Dissipation ◽  
Three Dimensional ◽  
3D Ic ◽  
Localized Heating ◽  
3D Integrated Circuits ◽  
Thermal Simulations

This paper presents full-chip scale detailed thermal simulations of three-dimensional (3D) integrated circuit (IC) stacks. The inter-layer dielectric (ILD) and inter-metal dielectric (IMD) materials inside 3D IC stacks may cause extensive localized heating. The influence of multiple layers of dielectrics on heat trapping inside the 3D stack is analyzed. Different methods to minimize such localized heating are studied. It is shown that the use of thermal vias is very effective in heat dissipation from the hot spots. Comparisons are made between several 3D IC configurations to verify these conclusions.

Thermoelectric Coolers for Hotspot Thermal Management of 3D Stacked Chips

2011 ◽  
Author(s):  
Matthew Redmond ◽  
Kavin Manickaraj ◽  
Owen Sullivan ◽  
Satish Kumar
Keyword(s):  
Integrated Circuits ◽  
Thermal Management ◽  
Power Density ◽  
Hot Spot ◽  
Thermal Contact ◽  
Three Dimensional ◽  
Heat Removal ◽  
Thermoelectric Coolers ◽  
Vertical Coupling ◽  
Spot Cooling

Three dimensional (3D) technologies with stacked chips have the potential to provide new chip architecture, improved device density, performance, efficiency, and bandwidth. Their increased power density also can become a daunting challenge for heat removal. Furthermore, power density can be highly non-uniform leading to time and space varying hotspots which can severely affect performance and reliability of the integrated circuits. Thus, it is important to mitigate thermal gradients on chip while considering the associated cooling costs. One method of thermal management currently under investigation is the use of superlattice thermoelectric coolers (TECs) which can be employed for on demand and localized cooling. In this paper, a detailed 3D thermal model of a stacked electronic package with two dies and four ultrathin integrated TECs is studied in order to investigate the efficacy of TECs in hot spot cooling for a 3D technology. We observe up to 14.6 °C of cooling at a hot spot inside the package by TECs. A strong vertical coupling has been observed between the TECs located in top and bottom dies. Bottom TECs can detrimentally heat the top hotspots in both steady state and transient operation. TECs need to be carefully placed inside the package to avoid such undesired heating. Thermal contact resistances between dies, inside the TEC module, and between the TEC and heat spreader are shown to have a crucial effect on TEC performance inside the package. We observed that square root current pulse can provide very efficient short-duration transient cooling at hotspots.

scholarly journals Evaluation of the Potential Electromagnetic Interference in Vertically Stacked 3D Integrated Circuits

2020 ◽  
Vol 10 (3) ◽  
pp. 748
Author(s):  
Dipesh Kapoor ◽  
Cher Ming Tan ◽  
Vivek Sangwan
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
Electromagnetic Interference ◽  
High Speed ◽  
High Performance ◽  
Near Field ◽  
Three Dimensional ◽  
3D Ic ◽  
Three Dimensional Integrated Circuit ◽  
The Impact

Advancements in the functionalities and operating frequencies of integrated circuits (IC) have led to the necessity of measuring their electromagnetic Interference (EMI). Three-dimensional integrated circuit (3D-IC) represents the current advancements for multi-functionalities, high speed, high performance, and low-power IC technology. While the thermal challenges of 3D-IC have been studied extensively, the influence of EMI among the stacked dies has not been investigated. With the decreasing spacing between the stacked dies, this EMI can become more severe. This work demonstrates the potential of EMI within a 3D-IC numerically, and determines the minimum distance between stack dies to reduce the impact of EMI from one another before they are fabricated. The limitations of using near field measurement for the EMI study in stacked dies 3D-IC are also illustrated.

Experimental Analysis Model of an Active Cooling Method for 3D-ICs Utilizing Multidimensional Configured Thermoelectric Coolers

2010 ◽  
Vol 132 (2) ◽  
Author(s):  
Huy N. Phan ◽  
Dereje Agonafer
Keyword(s):  
Integrated Circuits ◽  
Thermal Management ◽  
Heat Dissipation ◽  
Three Dimensional ◽  
Analysis Model ◽  
Thermoelectric Coolers ◽  
Active Cooling ◽  
3D Ics ◽  
Cooling Method ◽  
Memory Applications

Presently, stack dice are used widely as low-power memory applications because thermal management of 3D architecture such as high-power processors inherits many thermal challenges. Inadequate thermal management of three-dimensional integrated circuits (3D-ICs) leads to reduction in performance, reliability, and ultimately system catastrophic failure. Heat dissipation of 3D systems is highly nonuniform and nonunidirectional due to many factors such as power architectures, transistors packing density, and real estate available on the chip. In this study, the development of an experimental model of an active cooling method to cool a 25 W stack-dice to approximately 13°C utilizing a multidimensional configured thermoelectric will be presented.

High-Flux Thin Film Evaporation on Nanostructured Surfaces

2010 ◽  
Author(s):  
Rong Xiao ◽  
Kuang-Han Chu ◽  
Evelyn N. Wang
Keyword(s):  
Thin Film ◽  
Liquid Film ◽  
High Performance ◽  
Heat Dissipation ◽  
Heat Removal ◽  
High Heat ◽  
Back Side ◽  
Nanostructured Surfaces ◽  
Thin Film Evaporation ◽  
Film Evaporation

The heat generation rates of high performance electronics motivate the development of new thermal management solutions. Thin film evaporation with a jet impingement or spray system promise high heat fluxes up to 1000 W/cm2 with low thermal resistances. However, challenges with implementation currently limit the ability to reach the theoretical limits. In this work, we investigated the utilization of micro-/nanostructured surfaces to control the liquid film thickness and provide a sufficient liquid flow rate to achieve high heat removal rates. We developed a model to predict the propagation rates of the liquid film, which accounted for the curvature of the liquid meniscus. We also fabricated test devices with pillar diameters ranging from 500 nm to 10 μm, spacings of 3.5 μm to 10 μm, and heights of 5 μm to 15 μm, and validated the model with confocal microscopy and high speed imaging. Heaters and temperature sensors were also integrated onto the back side of the chip to investigate heat transfer performance. When heat was applied, the structures significantly enhanced the heat dissipation rates and reduced the thermal resistance. The heat dissipation rate was also found to be positively correlated to the propagation rate of the liquid film. However, surface fouling in the experiments led to challenges to maintain a stable liquid film, and decreased the heat removal capability. This work provides insights to designing micro-/nanostructured surfaces for thin film evaporation to meet the heat dissipation demands of future high performance electronic systems.

Electrical Interconnect and Microfluidic Cooling Within 3D ICs and Silicon Interposer

2014 ◽  
Author(s):  
Hanju Oh ◽  
Yue Zhang ◽  
Li Zheng ◽  
Muhannad S. Bakir
Keyword(s):  
Integrated Circuits ◽  
Thermal Gradient ◽  
Heat Dissipation ◽  
Three Dimensional ◽  
Heat Removal ◽  
3D Ic ◽  
Significant Challenge ◽  
3D Ics ◽  
Silicon Vias ◽  
First Time

Heat dissipation is a significant challenge for three-dimensional integrated circuits (3D IC) due to the lack of heat removal paths and increased power density. In this paper, a 3D IC system with an embedded microfluidic cooling heat sink (MFHS) is presented. In the proposed 3D IC system, high power tiers contain embedded MFHS and high-aspect ratio (23:1) through-silicon-vias (TSVs) routed through the integrated MFHS. In addition, each tier has dedicated solder-based microfluidic chip I/Os. Microfluidic cooling experiments of staggered micropin-fins with embedded TSVs are presented for the first time. Moreover, the lateral thermal gradient across a chip is analyzed with segmented heaters.

Sign in / Sign up

Export Citation Format

Share Document