Thermal Issues in Next Generation Integrated Circuits

2003 ◽  
Author(s):  
Siva Gurrum ◽  
Shivesh Suman ◽  
Yogendra Joshi ◽  
Andrei Fedorov
Keyword(s):  
Integrated Circuits ◽  
Thermal Management ◽  
Power Dissipation ◽  
High Performance ◽  
Electronic Devices ◽  
Heat Removal ◽  
Current Generation ◽  
Fundamental Limits ◽  
Convection Boundary ◽  
And Performance

Effective cooling of electronic chips is crucial for reliability and performance of electronic devices. Steadily increasing power dissipation in both devices and interconnects motivate the investigation of chip-centric thermal management as opposed to traditional package-centric solutions. In this work, we explore the fundamental limits for heat removal from a model chip for various configurations. Temperature rise when the chip is embedded in an infinite solid is computed for different thermal conductivities of the medium to pin down the best that can be achieved with conduction based thermal management. Next, a chip attached to a spreader plate with convection boundary condition on top was considered. A brief review of interface thermal resistances and partitioning of overall thermal resistance is presented for current generation microprocessors. Based upon the analysis it is concluded that far-term cooling solutions might necessitate integration with chip/interconnect-stack to meet the challenges. In addition, this would require concurrent thermal and electrical design/fabrication of future high-performance microprocessors.

Benchmarking Study on the Thermal Management Landscape for Three-Dimensional Integrated Circuits: From Back-Side to Volumetric Heat Removal

2016 ◽  
Vol 138 (1) ◽  
Author(s):  
Thomas Brunschwiler ◽  
Arvind Sridhar ◽  
Chin Lee Ong ◽  
Gerd Schlottig
Keyword(s):  
Integrated Circuits ◽  
Thermal Management ◽  
Integrated Circuit ◽  
Power Dissipation ◽  
High Performance ◽  
Heat Dissipation ◽  
Hybrid Approach ◽  
Three Dimensional ◽  
Heat Removal ◽  
Back Side

An overview of the thermal management landscape with focus on heat dissipation from three-dimensional (3D) chip stacks is provided in this study. Evolutionary and revolutionary topologies, such as single-side, dual-side, and finally, volumetric heat removal, are benchmarked with respect to a high-performance three-tier chip stack with an aggregate power dissipation of 672 W. The thermal budget of 50 K can be maintained by three topologies, namely: (1) dual-side cooling, implemented by a thermally active interposer, (2) interlayer cooling with four-port fluid delivery and drainage at 100 kPa pressure drop, and (3) a hybrid approach combining interlayer with embedded back-side cooling. Of all the heat-removal concepts, interlayer cooling is the only approach that scales with the number of dies in the chip stack and hence enables extreme 3D integration. However, the required size of the microchannels competes with the requirement of low through-silicon-via (TSV) heights and pitches. A scaling study was performed to derive the TSV pitch that is compatible with cooling channels to dissipate 150 W/cm2 per tier. An active integrated circuit (IC) area of 4 cm2 was considered, which had to be implemented on the varying tier count in the stack. A cuboid form factor of 2 mm × 4 mm × 2.55 mm results from a die count of 50. The resulting microchannels of 2 mm length allow small hydraulic diameters and thus a very high TSV density of 1837 1/mm2. The accumulated heat flux and the volumetric power dissipation are as high as 7.5 kW/cm2 and 29 kW/cm3, respectively.

Benchmarking Study on the Thermal Management Landscape for 3D ICs: From Back-Side to Volumetric Heat Removal

2015 ◽  
Author(s):  
Thomas Brunschwiler ◽  
Arvind Sridhar ◽  
Chin Lee Ong ◽  
Gerd Schlottig
Keyword(s):  
Thermal Management ◽  
Power Dissipation ◽  
High Performance ◽  
Heat Dissipation ◽  
Hybrid Approach ◽  
Heat Removal ◽  
Back Side ◽  
Cooling Channels ◽  
Fluid Delivery ◽  
Single Side

An overview of the thermal management landscape with focus on heat dissipation from 3D chip stacks is provided in this study. Evolutionary and revolutionary topologies, such as single-side, dual-side and, finally, volumetric heat removal, are benchmarked with respect to a high-performance three-tier chip stack with an aggregate power dissipation of 672 W. The thermal budget of 50 K can be maintained by three topologies, namely, 1) dual-side cooling, implemented by a thermally active interposer, 2) interlayer cooling with 4-port fluid delivery and drainage at 100 kPa pressure drop, and 3) a hybrid approach combining interlayer with embedded back-side cooling. Of all the heat-removal concepts, interlayer cooling is the only approach that scales with the number of dies in the chip stack and hence, enables extreme 3D integration. However, the required size of the microchannels competes with the requirement of low TSV heights and pitches. A scaling study was performed to derive the TSV pitch that is compatible with cooling channels to dissipate 150 W/cm2 per tier. An active IC area of 4 cm2 was considered, which had to be implemented on the varying tier count in the stack. A cuboid form factor of 2 mm × 4 mm × 2.55 mm results from a die count of 50. The resulting microchannels of 2 mm length allow small hydraulic diameters and thus a very high TSV density of 1837 1/mm2. The accumulated heat flux and the volumetric power dissipation are as high as 7.5 kW/cm2 and 29kW/cm3, respectively.

Buffer for High Performance in CNT Based VLSI Interconnects

2018 ◽  
Vol 24 (8) ◽  
pp. 5975-5981
Author(s):  
A Karthikeyan ◽  
P. S Mallick
Keyword(s):  
Integrated Circuits ◽  
Packing Density ◽  
Power Dissipation ◽  
High Performance ◽  
Critical Path ◽  
Vlsi Interconnects ◽  
Performance Constraints ◽  
Interconnect Delay ◽  
Interconnect Optimization ◽  
Technology Nodes

Integrated circuits (IC’s) are sized for higher performance and packing density. Interconnects are major components to carry signals between transistors. Interconnect delay increases due to increase in length of interconnect. Optimization of interconnects is more essential to improve the performance of integrated circuits. Repeater insertion is an important technique used in optimizing the performance of interconnects in integrated circuits. Repeaters have to be designed to satisfy the performance constraints. In this paper we have designed a new repeater using transistors and analyzed the performance at various bias levels. The Repeater design was implemented at various technology nodes using PTM models and Bulk CMOS. Delay and power dissipation are analyzed for various voltage levels and load levels using Spice simulations. The results show that the proposed repeater has lesser delay compared to the conventional repeater with an increase of power dissipation and they are more suitable for Critical path in VLSI interconnects. They can be applicable for CNT based VLSI interconnects.

A High Performance Submicrometer CMOS/SOI Technology Using Ultrathin Silicon Films on Simox

1987 ◽  
Vol 107 ◽  
Author(s):  
P.K. Vasudev ◽  
K.W. Terrill ◽  
S. Seymour
Keyword(s):  
Integrated Circuits ◽  
High Performance ◽  
Silicon Films ◽  
Ring Oscillator ◽  
Cmos Integrated Circuits ◽  
And Performance ◽  
High Transconductance ◽  
Soi Technology ◽  
Very High

AbstractThe use of ultrathin SIMOX wafers for fabricating submicrometer CMOS integrated circuits is described. It is demonstrated from ring oscillator speeds that properly designed devices can exhibit very high transconductance and performance superior to circuits using bulk Si.

HEAT, SPEED AND ERROR LIMITS OF MOORE'S LAW AT THE NANO SCALES

2006 ◽  
Vol 06 (02) ◽  
pp. L127-L131 ◽  
Author(s):  
YINGFENG LI ◽  
LASZLO B. KISH
Keyword(s):  
Power Dissipation ◽  
High Performance ◽  
Leakage Currents ◽  
Moore’S Law ◽  
Moore's Law ◽  
Saturation Limit ◽  
And Performance

The evolution of microprocessor miniaturization and performance, often described by Moore's law [1, 2], is close to the saturation limit. This paper discusses the limitation of the evolution of performance and minimization process for high performance microprocessors related to noise and power dissipation. In particular, the predictions provided in a previous paper [3] are refined in order to take into account the increasing effect of leakage currents on power dissipation.

scholarly journals 4-bit Carry Look Ahead Adder Using MGDI Technique

2021 ◽  
Vol 9 (9) ◽  
pp. 855-860
Author(s):  
Shaik Mahammad Ameer Afridi
Keyword(s):  
Integrated Circuits ◽  
Low Power ◽  
Power Dissipation ◽  
High Performance ◽  
Digital Signal ◽  
Vlsi Circuits ◽  
Digital Vlsi ◽  
Look Ahead ◽  
Energy Trade ◽  
Integral Role

Abstract: Today's high-performance processor is built with arithmetic logic units that add and subtract key components. Design considerations related to low power and high performance digital VLSI circuits have become more prevalent in today's world. In order to develop low-power and high-performance processors, the designers need to design their adder circuits with the required speed and power dissipation for their applications. This topic introduces the concept of a adder using MGDI Technique. The Exact Speculative Carry Look Ahead Adder the use of the Modified-GDI (Modified-Gate Diffusion Input) is cautioned in this work. The delay, location and energy trade off performs a integral role in VLSI. We already comprehend that designs which are of CMOS fashion occupy extra area might also eat extra strength consumption. The switching conduct of the circuit reason the heating up of integrated circuits affects the working stipulations of the purposeful unit. The adders are the most important parts of countless applications such as microprocessors, microcontrollers and digital signal processors and additionally in actual time applications. Hence it is necessary to minimize the adder blocks to format a perfect processor. This work is proposed on a 16 bit carry seem to be in advance adder is designed through using MGDI gate and 4T XOR gates and a speculator blocks. The proposed MGDI raise Look Ahead adder occupies 68% much less region and the strength consumption and the propagation extend additionally considerably reduces when in contrast to the traditional carry Look Ahead adder why because the variety transistors extensively reduces from 1448 (Conventional) to 456 (Proposed CLA). The simulation consequences of the proposed format carried out in Xilinx. Keywords: Delay, power dissipation, voltage, transistor sizing.

scholarly journals Recent Advances in Design and Preparation of Polymer-Based Thermal Management Material

Polymers ◽  
2021 ◽  
Vol 13 (16) ◽  
pp. 2797 ◽  
Author(s):  
Hongli Zhang ◽  
Tiezhu Shi ◽  
Aijie Ma
Keyword(s):  
Thermal Management ◽  
High Performance ◽  
Heat Dissipation ◽  
Electronic Devices ◽  
High Heat ◽  
Consumer Electronics ◽  
Recent Advances ◽  
Processing Strategies ◽  
Innovative Material ◽  
Processing Properties

The boosting of consumer electronics and 5G technology cause the continuous increment of the power density of electronic devices and lead to inevitable overheating problems, which reduces the operation efficiency and shortens the service life of electronic devices. Therefore, it is the primary task and a prerequisite to explore innovative material for meeting the requirement of high heat dissipation performance. In comparison with traditional thermal management material (e.g., ceramics and metals), the polymer-based thermal management material exhibit excellent mechanical, electrical insulation, chemical resistance and processing properties, and therefore is considered to be the most promising candidate to solve the heat dissipation problem. In this review, we summarized the recent advances of two typical polymer-based thermal management material including thermal-conduction thermal management material and thermal-storage thermal management material. Furtherly, the structural design, processing strategies and typical applications for two polymer-based thermal management materials were discussed. Finally, we proposed the challenges and prospects of the polymer-based thermal management material. This work presents new perspectives to develop advanced processing approaches and construction high-performance polymer-based thermal management material.

Micron-Level Actuators for Thermal Management of Microelectronic Devices

2007 ◽  
Author(s):  
Nurhak Erbas ◽  
Oktay Baysal
Keyword(s):  
Thermal Management ◽  
Power Dissipation ◽  
Transfer Rate ◽  
Operating Temperature ◽  
Electronic Devices ◽  
Synthetic Jet ◽  
Two Dimensional ◽  
Microelectronic Devices ◽  
Higher Power ◽  
Membrane Oscillations

Failure rates of electronic equipment depend on the operating temperature. Although demand for more effective cooling of electronic devices has increased in the last decades because of the microminiaturization in device sizes accompanied by higher power dissipation levels, there is still a challenge for engineers to attain improved reliability of thermal management for intermediate and low-heat-flux systems. In the present study, an innovative alternative method is proposed and a computational parametric study has been conducted. A single microchip is placed in a two-dimensional channel. Different synthetic jet configurations are designed as actuators in order to investigate their effectiveness for thermal management. The effect is that the actuator enhances mixing by imparting momentum to the channel flow thus manipulating the temperature field in a positive manner. The best control is achieved when the actuator is placed midway of the chip length and increasing the throat height. Also, using nozzle-like throat geometry increases the heat transfer rate from the microchip surface. Doubling the number of the actuators, optimally placing them, and phasing their membrane oscillations all improve the cooling.

scholarly journals Droplet-Based Microfluidic Thermal Management Methods for High Performance Electronic Devices

Micromachines ◽  
2019 ◽  
Vol 10 (2) ◽  
pp. 89 ◽  
Author(s):  
Zhibin Yan ◽  
Mingliang Jin ◽  
Zhengguang Li ◽  
Guofu Zhou ◽  
Lingling Shui
Keyword(s):  
Heat Flux ◽  
Thermal Management ◽  
High Performance ◽  
Rapid Development ◽  
Electronic Devices ◽  
High Heat ◽  
High Heat Flux ◽  
Electrowetting On Dielectric ◽  
Handling Methods ◽  
Cooling Methods

Advanced thermal management methods have been the key issues for the rapid development of the electronic industry following Moore’s law. Droplet-based microfluidic cooling technologies are considered as promising solutions to conquer the major challenges of high heat flux removal and nonuniform temperature distribution in confined spaces for high performance electronic devices. In this paper, we review the state-of-the-art droplet-based microfluidic cooling methods in the literature, including the basic theory of electrocapillarity, cooling applications of continuous electrowetting (CEW), electrowetting (EW) and electrowetting-on-dielectric (EWOD), and jumping droplet microfluidic liquid handling methods. The droplet-based microfluidic cooling methods have shown an attractive capability of microscale liquid manipulation and a relatively high heat flux removal for hot spots. Recommendations are made for further research to develop advanced liquid coolant materials and the optimization of system operation parameters.

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