Benchmarking Study on the Thermal Management Landscape for 3D ICs: From Back-Side to Volumetric Heat Removal

2015 ◽  
Author(s):  
Thomas Brunschwiler ◽  
Arvind Sridhar ◽  
Chin Lee Ong ◽  
Gerd Schlottig
Keyword(s):  
Thermal Management ◽  
Power Dissipation ◽  
High Performance ◽  
Heat Dissipation ◽  
Hybrid Approach ◽  
Heat Removal ◽  
Back Side ◽  
Cooling Channels ◽  
Fluid Delivery ◽  
Single Side

An overview of the thermal management landscape with focus on heat dissipation from 3D chip stacks is provided in this study. Evolutionary and revolutionary topologies, such as single-side, dual-side and, finally, volumetric heat removal, are benchmarked with respect to a high-performance three-tier chip stack with an aggregate power dissipation of 672 W. The thermal budget of 50 K can be maintained by three topologies, namely, 1) dual-side cooling, implemented by a thermally active interposer, 2) interlayer cooling with 4-port fluid delivery and drainage at 100 kPa pressure drop, and 3) a hybrid approach combining interlayer with embedded back-side cooling. Of all the heat-removal concepts, interlayer cooling is the only approach that scales with the number of dies in the chip stack and hence, enables extreme 3D integration. However, the required size of the microchannels competes with the requirement of low TSV heights and pitches. A scaling study was performed to derive the TSV pitch that is compatible with cooling channels to dissipate 150 W/cm2 per tier. An active IC area of 4 cm2 was considered, which had to be implemented on the varying tier count in the stack. A cuboid form factor of 2 mm × 4 mm × 2.55 mm results from a die count of 50. The resulting microchannels of 2 mm length allow small hydraulic diameters and thus a very high TSV density of 1837 1/mm2. The accumulated heat flux and the volumetric power dissipation are as high as 7.5 kW/cm2 and 29kW/cm3, respectively.

Benchmarking Study on the Thermal Management Landscape for Three-Dimensional Integrated Circuits: From Back-Side to Volumetric Heat Removal

2016 ◽  
Vol 138 (1) ◽  
Author(s):  
Thomas Brunschwiler ◽  
Arvind Sridhar ◽  
Chin Lee Ong ◽  
Gerd Schlottig
Keyword(s):  
Integrated Circuits ◽  
Thermal Management ◽  
Integrated Circuit ◽  
Power Dissipation ◽  
High Performance ◽  
Heat Dissipation ◽  
Hybrid Approach ◽  
Three Dimensional ◽  
Heat Removal ◽  
Back Side

An overview of the thermal management landscape with focus on heat dissipation from three-dimensional (3D) chip stacks is provided in this study. Evolutionary and revolutionary topologies, such as single-side, dual-side, and finally, volumetric heat removal, are benchmarked with respect to a high-performance three-tier chip stack with an aggregate power dissipation of 672 W. The thermal budget of 50 K can be maintained by three topologies, namely: (1) dual-side cooling, implemented by a thermally active interposer, (2) interlayer cooling with four-port fluid delivery and drainage at 100 kPa pressure drop, and (3) a hybrid approach combining interlayer with embedded back-side cooling. Of all the heat-removal concepts, interlayer cooling is the only approach that scales with the number of dies in the chip stack and hence enables extreme 3D integration. However, the required size of the microchannels competes with the requirement of low through-silicon-via (TSV) heights and pitches. A scaling study was performed to derive the TSV pitch that is compatible with cooling channels to dissipate 150 W/cm2 per tier. An active integrated circuit (IC) area of 4 cm2 was considered, which had to be implemented on the varying tier count in the stack. A cuboid form factor of 2 mm × 4 mm × 2.55 mm results from a die count of 50. The resulting microchannels of 2 mm length allow small hydraulic diameters and thus a very high TSV density of 1837 1/mm2. The accumulated heat flux and the volumetric power dissipation are as high as 7.5 kW/cm2 and 29 kW/cm3, respectively.

Thermal Issues in Next Generation Integrated Circuits

2003 ◽  
Author(s):  
Siva Gurrum ◽  
Shivesh Suman ◽  
Yogendra Joshi ◽  
Andrei Fedorov
Keyword(s):  
Integrated Circuits ◽  
Thermal Management ◽  
Power Dissipation ◽  
High Performance ◽  
Electronic Devices ◽  
Heat Removal ◽  
Current Generation ◽  
Fundamental Limits ◽  
Convection Boundary ◽  
And Performance

Effective cooling of electronic chips is crucial for reliability and performance of electronic devices. Steadily increasing power dissipation in both devices and interconnects motivate the investigation of chip-centric thermal management as opposed to traditional package-centric solutions. In this work, we explore the fundamental limits for heat removal from a model chip for various configurations. Temperature rise when the chip is embedded in an infinite solid is computed for different thermal conductivities of the medium to pin down the best that can be achieved with conduction based thermal management. Next, a chip attached to a spreader plate with convection boundary condition on top was considered. A brief review of interface thermal resistances and partitioning of overall thermal resistance is presented for current generation microprocessors. Based upon the analysis it is concluded that far-term cooling solutions might necessitate integration with chip/interconnect-stack to meet the challenges. In addition, this would require concurrent thermal and electrical design/fabrication of future high-performance microprocessors.

High-Flux Thin Film Evaporation on Nanostructured Surfaces

2010 ◽  
Author(s):  
Rong Xiao ◽  
Kuang-Han Chu ◽  
Evelyn N. Wang
Keyword(s):  
Thin Film ◽  
Liquid Film ◽  
High Performance ◽  
Heat Dissipation ◽  
Heat Removal ◽  
High Heat ◽  
Back Side ◽  
Nanostructured Surfaces ◽  
Thin Film Evaporation ◽  
Film Evaporation

The heat generation rates of high performance electronics motivate the development of new thermal management solutions. Thin film evaporation with a jet impingement or spray system promise high heat fluxes up to 1000 W/cm2 with low thermal resistances. However, challenges with implementation currently limit the ability to reach the theoretical limits. In this work, we investigated the utilization of micro-/nanostructured surfaces to control the liquid film thickness and provide a sufficient liquid flow rate to achieve high heat removal rates. We developed a model to predict the propagation rates of the liquid film, which accounted for the curvature of the liquid meniscus. We also fabricated test devices with pillar diameters ranging from 500 nm to 10 μm, spacings of 3.5 μm to 10 μm, and heights of 5 μm to 15 μm, and validated the model with confocal microscopy and high speed imaging. Heaters and temperature sensors were also integrated onto the back side of the chip to investigate heat transfer performance. When heat was applied, the structures significantly enhanced the heat dissipation rates and reduced the thermal resistance. The heat dissipation rate was also found to be positively correlated to the propagation rate of the liquid film. However, surface fouling in the experiments led to challenges to maintain a stable liquid film, and decreased the heat removal capability. This work provides insights to designing micro-/nanostructured surfaces for thin film evaporation to meet the heat dissipation demands of future high performance electronic systems.

scholarly journals Recent Advances in Design and Preparation of Polymer-Based Thermal Management Material

Polymers ◽  
2021 ◽  
Vol 13 (16) ◽  
pp. 2797 ◽  
Author(s):  
Hongli Zhang ◽  
Tiezhu Shi ◽  
Aijie Ma
Keyword(s):  
Thermal Management ◽  
High Performance ◽  
Heat Dissipation ◽  
Electronic Devices ◽  
High Heat ◽  
Consumer Electronics ◽  
Recent Advances ◽  
Processing Strategies ◽  
Innovative Material ◽  
Processing Properties

The boosting of consumer electronics and 5G technology cause the continuous increment of the power density of electronic devices and lead to inevitable overheating problems, which reduces the operation efficiency and shortens the service life of electronic devices. Therefore, it is the primary task and a prerequisite to explore innovative material for meeting the requirement of high heat dissipation performance. In comparison with traditional thermal management material (e.g., ceramics and metals), the polymer-based thermal management material exhibit excellent mechanical, electrical insulation, chemical resistance and processing properties, and therefore is considered to be the most promising candidate to solve the heat dissipation problem. In this review, we summarized the recent advances of two typical polymer-based thermal management material including thermal-conduction thermal management material and thermal-storage thermal management material. Furtherly, the structural design, processing strategies and typical applications for two polymer-based thermal management materials were discussed. Finally, we proposed the challenges and prospects of the polymer-based thermal management material. This work presents new perspectives to develop advanced processing approaches and construction high-performance polymer-based thermal management material.

Compact Transient Thermal Model of Microfluidically Cooled Three-Dimensional Stacked Chips With Pin-Fin Enhanced Microgap

2021 ◽  
Vol 143 (3) ◽  
Author(s):  
Yuanchen Hu ◽  
Md Obaidul Hossen ◽  
Zhimin Wan ◽  
Muhannad S. Bakir ◽  
Yogendra Joshi
Keyword(s):  
Heat Transfer ◽  
Integrated Circuit ◽  
High Performance ◽  
Heat Dissipation ◽  
Three Dimensional ◽  
Heat Removal ◽  
Power Estimation ◽  
Leakage Power ◽  
Pin Fin ◽  
Pin Fins

Abstract Three-dimensional (3D) stacked integrated circuit (SIC) chips are one of the most promising technologies to achieve compact, high-performance, and energy-efficient architectures. However, they face a heat dissipation bottleneck due to the increased volumetric heat generation and reduced surface area. Previous work demonstrated that pin-fin enhanced microgap cooling, which provides fluidic cooling between layers could potentially address the heat dissipation challenge. In this paper, a compact multitier pin-fin single-phase liquid cooling model has been established for both steady-state and transient conditions. The model considers heat transfer between layers via pin-fins, as well as the convective heat removal in each tier. Spatially and temporally varying heat flux distribution, or power map, in each tier can be modeled. The cooling fluid can have different pumping power and directions for each tier. The model predictions are compared with detailed simulations using computational fluid dynamics/heat transfer (CFD/HT). The compact model is found to run 120–600 times faster than the CFD/HT model, while providing acceptable accuracy. Actual leakage power estimation is performed in this codesign model, which is an important contribution for codesign of 3D-SICs. For the simulated cases, temperatures could decrease 3% when leakage power estimation is adopted. This model could be used as electrical-thermal codesign tool to optimize thermal management and reduce leakage power.

A Model Predictive Framework for Thermal Management of Aircraft

2015 ◽  
Author(s):  
Timothy O. Deppen ◽  
Joel E. Hey ◽  
Andrew G. Alleyne ◽  
Timothy S. Fisher
Keyword(s):  
Thermal Management ◽  
High Performance ◽  
Heat Dissipation ◽  
Electrical Power ◽  
Electrical Equipment ◽  
Thermal Loads ◽  
Case Scenario ◽  
Worst Case ◽  
Order Of Magnitude ◽  
Transient Thermal

The challenge of managing heat dissipation and enforcing operational constraints on temperature within a high-performance tactical aircraft is considered. For these systems, power density of the electrical equipment and the associated thermal loads are quickly outpacing the means of conventional thermal management systems (TMS) to provide on-demand cooling and in order to prevent thermal run away. The next generation of tactical aircraft is projected to include an order of magnitude greater thermal and electrical power magnitudes, and the time scale over which thermal loads will change is expected to shrink. To meet this rapidly evolving challenge, designing a TMS for the “worst case” scenario based on a steady-state thermal analysis will be infeasible. Rather, a holistic systems perspective is needed with new control methodologies that capture and even exploit the transient thermal behavior. To this end, a model predictive control strategy is presented that utilizes preview of upcoming loads and disturbances to prevent violation of temperature constraints. A simulation case study demonstrates that the predictive thermal controller can dramatically reduce constraint violations while reducing the work required by the TMS when compared to a cascaded PI feedback controller.

scholarly journals OS Level Power Optimization in LCMP

2019 ◽  
Vol 8 (4) ◽  
pp. 10089-10092
Keyword(s):  
Power Consumption ◽  
Power Dissipation ◽  
High Performance ◽  
Large Scale ◽  
Heat Dissipation ◽  
Power Optimization ◽  
Reducing Power ◽  
System Throughput ◽  
Thread Migration ◽  
Computing Power

With the increasing levels of transistor count and clock rate of microprocessors there is a significant increase in power dissipation. Reducing power consumption in both high power consumption and high performance has developed into one of the main target in designing a system for various devices. As the chip multiprocessor (CMP) are integrating more cores on the die, it will leads to the extent of Large scale CMP (LCMP) architectures with potentially hundreds of thread on the die and thousands of cores. Therefore, we proposed an approach of OS level power optimization in LCMP to optimize the heat dissipation rate and increase computing power under some considerations. To satisfy the main goal of our work, the heat dissipation should be optimizing with increase in computing power. The approach of optimizing the heat dissipation is done at the synthesis level. There are three approaches for modifying the synthetic benchmark: Singly Synthesis, Hierarchical Synthesis and Group Synthesis. The result is that the power dissipation of Group synthesis is equally distributed without giving more loads to only one processor as compared to Hierarchical Synthesis and Singly Synthesis. Therefore, from our result we can conclude that in Group Synthesis power is equally distributed hence heat dissipation is optimized. The future work will be to further optimize the result of the Synthesis level using thread migration. Thread Migration can increase the system throughput; it relies on multiple cores that vary in performance capabilities

Modeling and Analysis for Thermal Management in Gallium Nitride HEMTs Using Microfluidic Cooling

2016 ◽  
Vol 139 (1) ◽  
Author(s):  
Gunjan Agarwal ◽  
Thomas Kazior ◽  
Thomas Kenny ◽  
Dana Weinstein
Keyword(s):  
Gallium Nitride ◽  
Thermal Management ◽  
Transmission Lines ◽  
High Performance ◽  
High Electron Mobility Transistors ◽  
High Electron ◽  
Element Analysis ◽  
Modeling And Analysis ◽  
Cooling Channels ◽  
Rf Systems

In this paper, thermal management in GaN (gallium nitride) based microelectronic devices is addressed using microfluidic cooling. Numerical modeling is done using finite element analysis (FEA), and the results for temperature distribution are presented for a system comprising multiple cooling channels underneath GaN high-electron mobility transistors (HEMTs). The thermal stack modeled is compatible for heterogeneous integration with conventional silicon-based CMOS devices. Parametric studies for cooling performance are done over a range of geometric and flow factors to determine the optimal cooling configuration within the specified constraints. A power dissipation of 2–4 W/mm is modeled along each HEMT finger in the proposed configuration. The cooling arrangements modeled here hold promising potential for implementation in high-performance radio-frequency (RF) systems for power amplifiers, transmission lines, and other applications in defense and military.

Microwave Module Thermal Considerations for Future Higher Powered MMICs in Phased Array Radars

2003 ◽  
Author(s):  
James S. Wilson
Keyword(s):  
Thermal Management ◽  
Temperature Difference ◽  
Integrated Circuit ◽  
Heat Dissipation ◽  
Phased Array ◽  
Waste Heat ◽  
Heat Removal ◽  
Thermal Design ◽  
Rf Power ◽  
Phased Array Radar

Advances in RF power generation capability at the device level will soon force a change in phased array radar thermal management. The efficiency in converting electrical power into transmitted power is not increasing as rapidly which means that higher RF power generating devices also dissipate more heat. Removing this waste heat creates several thermal challenges including the topic of this paper, namely thermal issues at the die and package level. A comparison of the temperature differences between the junction and ambient shows that even at present heat dissipation levels, the temperature difference at the integrated circuit level is already a significant fraction of the total rise. Further increases in the device level heat dissipation will increase the temperature difference at the integrated circuit level to nearly unmanageable levels unless device-level design changes are made. Maintaining acceptable junction temperature levels will require lower device mounting surface temperatures or some thermally better method of die attachment and heat removal. Dividing the thermal management of a phased array radar into two portions (integrated circuit level and everything else) reveals that while thermal improvements at the system and packaging level are useful for near-future radar designs, thermal design and management at the device and package levels are crucial.

Cooling of High-Performance Server Modules Using Direct Immersion

2012 ◽  
Author(s):  
Aravind Sridhar ◽  
Sarah Styslinger ◽  
Christopher Duron ◽  
Sushil H. Bhavnani ◽  
Roy W. Knight ◽  
...  
Keyword(s):  
Heat Flux ◽  
High Speed ◽  
High Performance ◽  
Heat Dissipation ◽  
Heat Removal ◽  
Liquid Pool ◽  
Circuit Board ◽  
Air Cooling ◽  
High Speed Imaging ◽  
Close Proximity

An alternative to air-cooling of high performance computing equipment is presented. Heat removal via pool boiling in FC-72 was tested. Tests were conducted on a multichip module using 1.8 cm × 1.8 cm test die with multiple thermal test cells with temperature sensing capability. Measurements with the bare silicon die in direct contact with the fluid are reported. Additional testing included the test die directly indium-attached to copper heat spreaders having surface treatments. A screen-printed sintered boiling-enhanced surface (4 cm × 4 cm) was evaluated. Tests were conducted on an array of five die. Parameters tested include heat flux levels, dielectric liquid pool conditions (saturated or subcooled), and effect of neighboring die. Information was gathered on surface temperatures for a range of heat flux values up to 12 W/cm2. The highest heat dissipated from a circuit board with five bare die was 195 W (39 W per die). Addition of the heat spreader allowed heat dissipation of up to 740 W (from a five-die array). High-speed imaging was also acquired to help examine detailed information on the boiling process. Numerical modeling indicated that placing multiple boards in close proximity to each other did not degrade performance until board spacing was reduced to 3 mm.

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