Design rule optimization for via layers of multiple patterning solution at 7nm technology node

Test time reduction is a prominent challenge in scan based Design For Testability (DFT) architectures for cost effective test. Reliability and testability both are main objectives for DFT in today’s VLSI design. In this paper, we have proposed multiple standard test control point insertion technique for 7nm technology node. The design was tested on 7828 sequential cells. We have compared results of following three Design Rule Check (DRC) (1) Scan DRC (2) Clock Scan DRC (3) Multiple standard test control point insertion DRC. We have used software tool Synopsys TetraMAX ATPG, Synopsys DFTMAX and Synopsys DFT compiler to verify the design. It has been observed that multiple standard test control point insertion DRC takes minimum time to check design of 7828 sequential cells.

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An integral injector-victim current transfer model for latchup design rule optimization

2018 IEEE International Reliability Physics Symposium (IRPS) ◽

10.1109/irps.2018.8353549 ◽

2018 ◽

Cited By ~ 1

Author(s):

Guido Quax ◽

Theo Smedes

Keyword(s):

Design Rule ◽

Transfer Model ◽

Current Transfer ◽

Rule Optimization

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Failure Types & Analysis In Cu Process Development of Design-Rule 0.18μm CPU

ISTFA 2001: Conference Proceedings from the 27th International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2001p0115 ◽

2001 ◽

Author(s):

DongKwon Jeong ◽

JuHyeon Ahn ◽

SangIn Lee ◽

JooHyuk Chung ◽

ByungLyul Park ◽

...

Keyword(s):

Process Improvement ◽

Process Development ◽

Metal Corrosion ◽

Pass Rate ◽

Design Rule ◽

The Novel ◽

Corrosion Loss ◽

Barrier Metal ◽

Development State ◽

Failure Types

Abstract This paper presents the problems, the solutions, and the development state of the novel 0.18 μm Cu Metal Process through failure analysis of the Alpha CPU under development at Samsung Electronics. The presented problems include : “Via Bottom Lifting” induced by the Cu Via void, “Via Bottom dissociation” due to the IMD stress, “Via side dissociation” due to the poor formation of the Barrier Metal, “Via short/not-open failure” due to the IMD lifting, and Cu metal Corrosion/Loss. The analysis was carried out on the Via Contact Test Chain Patterns, using the “Electron (ION) Charge Up” method. After carefully analyzing each of the failure types, process improvement efforts followed. As a result, the pass rate of the via contact Rc was brought up from a mere 20% to 95%, and the device speed higher than 1.1 GHz was achieved, which surpasses the target speed of 1 GHz.

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Root Cause Analysis for Pin Leakage

ISTFA 2016: Conference Proceedings from the 42nd International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2016p0217 ◽

2016 ◽

Author(s):

Zhigang Song ◽

Jochonia Nxumalo ◽

Manuel Villalobos ◽

Sweta Pendyala

Keyword(s):

Failure Analysis ◽

Root Cause Analysis ◽

Advanced Technology ◽

Process Step ◽

Cause Analysis ◽

Hard Mask ◽

Technology Node ◽

Root Cause ◽

Tools And Techniques

Abstract Pin leakage continues to be on the list of top yield detractors for microelectronics devices. It is simply manifested as elevated current with one pin or several pins during pin continuity test. Although many techniques are capable to globally localize the fault of pin leakage, root cause analysis and identification for it are still very challenging with today’s advanced failure analysis tools and techniques. It is because pin leakage can be caused by any type of defect, at any layer in the device and at any process step. This paper presents a case study to demonstrate how to combine multiple techniques to accurately identify the root cause of a pin leakage issue for a device manufactured using advanced technology node. The root cause was identified as under-etch issue during P+ implantation hard mask opening for ESD protection diode, causing P+ implantation missing, which was responsible for the nearly ohmic type pin leakage.

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РАЗРАБОТКА ПРОТОТИПА ПРОГРАММНОГО МОДУЛЯ АВТОМАТИЗИРОВАННОЙ ГЕНЕРАЦИИ КВАЛИФИКАЦИОННЫХ ЯЧЕЕК ДЛЯ КОНТРОЛЯ ПРАВИЛ ПРОЕКТИРОВАНИЯ ИС

Nanoindustry Russia ◽

10.22184/1993-8578.2020.13.3s.721.725 ◽

2020 ◽

Vol 96 (3s) ◽

pp. 721-725

Author(s):

Ф.С. Золотухин ◽

А.С. Надин ◽

И.Е. Трифанихина

Keyword(s):

Industrial Design ◽

Automated Design ◽

Design Rule ◽

Software Module ◽

The Real ◽

Rule Checking ◽

Design Rule Checking

Разработан прототип программного модуля генератора квалификационных ячеек для автоматизированного контроля геометрических правил проектирования DRC. Проведено тестирование прототипа генератора в реальных рабочих условиях проектирования. The paper presents a prototype of software module of the QA-cells Generator for automated Design Rule Checking. The QA-Cells Generator has been tested in the real workplace within actual microelectronic industrial design.

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CDM Protection Test Structure for I/O Cells in a Submicronic Technology

Electronics ◽

10.3390/electronics10040443 ◽

2021 ◽

Vol 10 (4) ◽

pp. 443

Author(s):

Mihaela-Daniela Dobre ◽

Philippe Coll ◽

Gheorghe Brezeanu

Keyword(s):

Electrostatic Discharge ◽

New Technology ◽

Test Chip ◽

Technology Node ◽

Ground Resistance ◽

Maximum Resistance ◽

Device Model ◽

Protection Method ◽

Esd Protection ◽

Protection Devices

This paper proposes an investigation of a CDM (charge device model) electrostatic discharge (ESD) protection method used in submicronic input–output (I/O) structures. The modeling of the commonly used ESD protection devices as well as the modeling of the breakdown caused by ESD is not accurate using traditional commercial tools, hence the need for test-chip implementation, whenever a new technology node is used in production. The proposed method involves defining, implementing, testing, and concluding on one test-chip structure named generically “CDM ground resistance”. The structure assesses the maximum ground resistance allowed for the considered technology for which CDM protection is assured. The findings are important because they will be actively used as CDM protection for all I/O structures developed in the considered submicronic technology node. The paper will conclude on the constraints in terms of maximum resistance of ground metal track allowed to be CDM protected.

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