Novel Multiplexer Design Using Multi-State Spatial Wavefunction-Switched (SWS) FETs

2015 ◽  
Vol 24 (03n04) ◽  
pp. 1520011 ◽  
Author(s):  
Pial Mirdha ◽  
Murali Lingalugari ◽  
Evan K. Heller ◽  
John A. Chandy ◽  
Faquir C. Jain
Keyword(s):  
Quantum Wells ◽  
Gate Voltage ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Cmos Technology ◽  
Logic Device ◽  
Coupled Quantum Wells ◽  
Conduction Mode

In this paper, we propose a multiplexer design based on use of a twin channel and twin drain spatial wavefunction-switched field-effect transistors (SWSFETs). SWSFET comprises of vertically stacked coupled quantum wells devices, which are the channels, where depending on the gate voltage only one of the channels is in conduction mode. Using SWSFET in multi-channel and single drain configuration operates as a multi-valued logic device. 2:1 and 4:2 multiplexer designs are proposed which are compatible with current CMOS technology and with all SWSFET. Both designs lead to greater than 4X reduction in transistor count. Ngspice simulation of circuits is also presented.

scholarly journals Growth of high-quality semiconducting tellurium films for high-performance p-channel field-effect transistors with wafer-scale uniformity

2022 ◽  
Vol 6 (1) ◽  
Author(s):  
Taikyu Kim ◽  
Cheol Hee Choi ◽  
Pilgyu Byeon ◽  
Miso Lee ◽  
Aeran Song ◽  
...  
Keyword(s):  
Field Effect ◽  
Physical Vapor Deposition ◽  
High Performance ◽  
Supply Voltage ◽  
Field Effect Transistors ◽  
Low Cost ◽  
Three Dimensional ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Wafer Scale

AbstractAchieving high-performance p-type semiconductors has been considered one of the most challenging tasks for three-dimensional vertically integrated nanoelectronics. Although many candidates have been presented to date, the facile and scalable realization of high-mobility p-channel field-effect transistors (FETs) is still elusive. Here, we report a high-performance p-channel tellurium (Te) FET fabricated through physical vapor deposition at room temperature. A growth route involving Te deposition by sputtering, oxidation and subsequent reduction to an elemental Te film through alumina encapsulation allows the resulting p-channel FET to exhibit a high field-effect mobility of 30.9 cm2 V−1 s−1 and an ION/OFF ratio of 5.8 × 105 with 4-inch wafer-scale integrity on a SiO2/Si substrate. Complementary metal-oxide semiconductor (CMOS) inverters using In-Ga-Zn-O and 4-nm-thick Te channels show a remarkably high gain of ~75.2 and great noise margins at small supply voltage of 3 V. We believe that this low-cost and high-performance Te layer can pave the way for future CMOS technology enabling monolithic three-dimensional integration.

Inverter design with positive feedback field-effect transistors

2021 ◽  
Author(s):  
Changhoon Lee ◽  
Changwoo Han ◽  
Changhwan Shin
Keyword(s):  
Positive Feedback ◽  
Computer Aided Design ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Feedback Mechanism ◽  
Silicon On Insulator ◽  
Logic Device ◽  
Device Applications ◽  
Positive Feedback Mechanism ◽  
Switching Devices

Abstract As the physical size of semiconductor devices continues to be aggressively scaled down, feedback field-effect transistors (FBFET) with a positive feedback mechanism among a few promising steep switching devices have received attention as next-generation switching devices. Conventional FBFETs have been studied to explore their device performance. However, this has been restricted to the case of single FBFET; basic circuit designs with FBFETs have not been investigated extensively. In this work, we propose an inverter circuit design with silicon-on-insulator (SOI) FBFETs; we verified this inverter design with mixed-mode technology computer-aided design simulation. The basic principles and mechanisms for designing FBFET inverter circuits are explained because their configuration is different from conventional inverters. In addition, the device parameters necessary to optimize circuit construction are introduced for logic device applications.

scholarly journals Investigation of Monolithic 3D Integrated Circuit Inverter with Feedback Field Effect Transistors Using TCAD Simulation

Micromachines ◽  
2020 ◽  
Vol 11 (9) ◽  
pp. 852
Author(s):  
Jong Hyeok Oh ◽  
Yun Seop Yu
Keyword(s):  
Integrated Circuit ◽  
Computer Aided Design ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Electrical Coupling ◽  
Propagation Delay ◽  
Channel Length ◽  
Memory Window ◽  
Switching Voltage ◽  
Logic Device

The optimal structure and process for the feedback field-effect transistor (FBFET) to operate as a logic device are investigated by using a technology computer-aided design mixed-mode simulator. To minimize the memory window of the FBFET, the channel length (Lch), thickness of silicon body (Tsi), and doping concentration (Nch) of the channel region below the gate are adjusted. As a result, the memory window increases as Lch and Tsi increase, and the memory window is minimum when Nch is approximately 9 × 1019 cm−3. The electrical coupling between the top and bottom tiers of a monolithic 3-dimensional inverter (M3DINV) consisting of an n-type FBFET located at the top tier and a p-type FBFET located at the bottom tier is also investigated. In the M3DINV, we investigate variation of switching voltage with respect to voltage transfer characteristics (VTC), with different thickness values of interlayer dielectrics (TILD), Tsi, Lch, and Nch. The variation of propagation delay of the M3DINV with different TILD, Tsi, Lch, and Nch is also investigated. As a result, the electrical coupling between the stacked FBFETs by TILD can be neglected. The switching voltage gaps increase as Lch and Tsi increase and decrease, respectively. Furthermore, the slopes of VTC of M3DINV increase as Tsi and Nch increase. For transient response, tpHL decrease as Lch, Tsi, and Nch increase, but tpLH increase as Lch and Tsi increase and it is almost the same for Nch.

Cryogenic field effect transistors using strained silicon quantum wells in Si:SiGe heterostructures grown by APCVD

2001 ◽  
Vol 87 (3) ◽  
pp. 277-281 ◽  
Author(s):  
M.J Rack ◽  
T.J Thornton ◽  
D.K Ferry ◽  
Jeff Roberts ◽  
Richard C Westhoff ◽  
...  
Keyword(s):  
Quantum Wells ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Strained Silicon
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