Design of Clock and Ramp Generator Circuit Framework with 0.9V Low Operational Voltage

2013 ◽  
Vol 284-287 ◽  
pp. 2502-2508
Author(s):  
Rong Jong Wai ◽  
Jun Jie Liaw
Keyword(s):  
Threshold Voltage ◽  
Pulse Width Modulation ◽  
Low Voltage ◽  
Clean Energy ◽  
Oxide Semiconductor ◽  
Operational Amplifiers ◽  
Cmos Process ◽  
Clock Frequency ◽  
Ramp Generator ◽  
Generator Circuit

In this study, a new clock and ramp generator circuit framework with a 0.9V low operational voltage is designed for the voltage-mode/current-mode-controlled power management integrated chip of a DC-DC converter. In conventional clock and ramp generator circuit with operational amplifiers, its operational voltage is limited to be over 1.5V because of the problem of a higher threshold voltage in the metal-oxide-semiconductor field-effect transistor (MOSFET). As a result, it can not work well for a pulse-width-modulation DC-DC converter when a below 1V low-voltage single-cell clean-energy power source is applied. This newly-design clock and ramp generator circuit framework without operational amplifiers is investigated to cope with the limitation of the threshold voltage in the MOSFET. Therefore, the corresponding chip size and power consumption can be reduced. Moreover, this circuit still has the functions of adjustable clock frequency and ramp slope. In addition, numerical simulations by the HSPICE software and experimental results by a real chip fabricated in the TSMC 1P6M 0.18µm CMOS process are given to verify the effectiveness of the proposed circuit to produce the clock and ramp waveforms.

scholarly journals Active EMI Reduction Using Chaotic Modulation in a Buck Converter with Relaxed Output LC Filter

Electronics ◽  
2018 ◽  
Vol 7 (10) ◽  
pp. 254 ◽  
Author(s):  
Van Nguyen ◽  
Hai Huynh ◽  
SoYoung Kim ◽  
Hanjung Song
Keyword(s):  
Electromagnetic Interference ◽  
Power Efficiency ◽  
Pulse Width Modulation ◽  
Buck Converter ◽  
Oxide Semiconductor ◽  
Switching Frequency ◽  
Cmos Process ◽  
Reference Case ◽  
Ramp Generator ◽  
Chaotic Mode

DC-DC buck converters are widely used in portable applications because of their high power efficiency. However, their inherent fast switching releases electromagnetic emissions, making them prominent sources of electromagnetic interference (EMI). This paper proposes a voltage-controlled buck converter that reduces EMI by using a chaotic pulse-width modulation (PWM) technique based on a chaotic triangular ramp generator. The chaotic triangular ramp generator is constructed from a simple on-chip chaotic circuit linked with a symmetrically triangular ramp circuit. The proposed converter can thus operate in the chaotic mode reducing the EMI without requiring any EMI filters. Additionally, using the triangular ramp signal can relax the requirement for a large LC output filter in chaotic mode. The effectiveness of the proposed scheme was experimentally verified with a chaotic triangular ramp generator embedded in a voltage-mode controller buck converter using a 0.18 µm Complementary Metal Oxide Semiconductor (CMOS) process. The measurement results from a prototype showed that the EMI improvement from the proposed scheme is approximately 14.53 dB at the fundamental switching frequency with respect to the standard fixed-frequency PWM reference case.

Output Voltage Sampling Circuit for Discontinuous Conduction Mode Flyback Pulse-Width Modulation Controller

2016 ◽  
Vol 25 (11) ◽  
pp. 1650140 ◽  
Author(s):  
Ling-Feng Shi ◽  
Zhen-Bo Shi ◽  
Sen Chen ◽  
Jian-Hui Xun
Keyword(s):  
Pulse Width ◽  
Output Voltage ◽  
Pulse Width Modulation ◽  
Low Voltage ◽  
Low Cost ◽  
Complementary Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Discharge Time ◽  
Constant Output

Primary-side controlled pulse-width modulation (PWM) flyback converter has been widely used in low-power and low-voltage products for its simple structure and low cost. This paper presents a novel output voltage sampling circuit which considers the influence of the rectifier diode current on the output voltage sampling. The output voltage sampling circuit samples the output voltage at 85% of the secondary inductance discharge time [Formula: see text] of last cycle, which improves the accuracy of the output voltage sampling circuit. Besides, the circuit can also sample the secondary inductance discharge time [Formula: see text]. Finally, a chip has been fabricated in 0.6[Formula: see text][Formula: see text]m complementary metal-oxide semiconductor (CMOS) process, which is used in the presented output voltage sampling circuit in its internal circuit to simple output voltage and achieve constant output voltage.

scholarly journals Design Strategies and Architectures for Ultra-Low-Voltage Delta-Sigma ADCs

Electronics ◽  
2021 ◽  
Vol 10 (10) ◽  
pp. 1156
Author(s):  
Lorenzo Benvenuti ◽  
Alessandro Catania ◽  
Giuseppe Manfredini ◽  
Andrea Ria ◽  
Massimo Piotto ◽  
...  
Keyword(s):  
Low Voltage ◽  
Flicker Noise ◽  
Supply Voltage ◽  
Cmos Process ◽  
Clock Frequency ◽  
Design Environment ◽  
Ultra Low Power ◽  
Analog Cmos ◽  
Gain Error ◽  
Dc Gain

The design of ultra-low voltage analog CMOS integrated circuits requires ad hoc solutions to counteract the severe limitations introduced by the reduced voltage headroom. A popular approach is represented by inverter-based topologies, which however may suffer from reduced finite DC gain, thus limiting the accuracy and the resolutions of pivotal circuits like analog-to-digital converters. In this work, we discuss the effects of finite DC gain on ultra-low voltage ΔΣ modulators, focusing on the converter gain error. We propose an ultra-low voltage, ultra-low power, inverter-based ΔΣ modulator with reduced finite-DC-gain sensitivity. The modulator employs a two-stage, high DC-gain, switched-capacitor integrator that applies a correlated double sampling technique for offset cancellation and flicker noise reduction; it also makes use of an amplifier that implements a novel common-mode stabilization loop. The modulator was designed with the UMC 0.18 μm CMOS process to operate with a supply voltage of 0.3 V. It was validated by means of electrical simulations using the CadenceTM design environment. The achieved SNDR was 73 dB, with a bandwidth of 640 Hz, and a clock frequency of 164 kHz, consuming only 200.5 nW. It achieves a Schreier Figure of Merit of 168.1 dB. The proposed modulator is also able to work with lower supply voltages down to 0.15 V with the same resolution and a lower power consumption despite of a lower bandwidth. These characteristics make this design very appealing in sensor interfaces powered by energy harvesting sources.

scholarly journals A Novel Ultrasonic TOF Ranging System Using AlN Based PMUTs

Micromachines ◽  
2021 ◽  
Vol 12 (3) ◽  
pp. 284
Author(s):  
Yihsiang Chiu ◽  
Chen Wang ◽  
Dan Gong ◽  
Nan Li ◽  
Shenglin Ma ◽  
...  
Keyword(s):  
Clock Cycle ◽  
High Accuracy ◽  
Ultrasonic Waves ◽  
Oxide Semiconductor ◽  
Average Error ◽  
Cmos Process ◽  
Clock Frequency ◽  
Time Frequency ◽  
Range Finding ◽  
Wide Range

This paper presents a high-accuracy complementary metal oxide semiconductor (CMOS) driven ultrasonic ranging system based on air coupled aluminum nitride (AlN) based piezoelectric micromachined ultrasonic transducers (PMUTs) using time of flight (TOF). The mode shape and the time-frequency characteristics of PMUTs are simulated and analyzed. Two pieces of PMUTs with a frequency of 97 kHz and 96 kHz are applied. One is used to transmit and the other is used to receive ultrasonic waves. The Time to Digital Converter circuit (TDC), correlating the clock frequency with sound velocity, is utilized for range finding via TOF calculated from the system clock cycle. An application specific integrated circuit (ASIC) chip is designed and fabricated on a 0.18 μm CMOS process to acquire data from the PMUT. Compared to state of the art, the developed ranging system features a wide range and high accuracy, which allows to measure the range of 50 cm with an average error of 0.63 mm. AlN based PMUT is a promising candidate for an integrated portable ranging system.

Realization of Fractional-Order Double-Scroll Chaotic System Using Operational Transconductance Amplifier (OTA)

2017 ◽  
Vol 27 (01) ◽  
pp. 1850006 ◽  
Author(s):  
Mohammad Rafiq Dar ◽  
Nasir Ali Kant ◽  
Farooq Ahmad Khanday
Keyword(s):  
Fractional Order ◽  
Chaotic System ◽  
Low Voltage ◽  
Complementary Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Operational Transconductance Amplifiers ◽  
System A ◽  
Transconductance Amplifier ◽  
Theoretical Predictions

Realization of fractional-order double-scroll chaotic system using Operational Transconductance Amplifiers (OTAs) as active elements are presented in this paper. The fractional-order double-scroll chaotic system has been studied before as well using passive RC-ladder and tree-based structures but in this paper the requisite fractional-order integration has been accomplished through an integer-order multiple-feedback topology. As compared to double or multiple scroll chaotic systems existing in the open literature, the proposed realization offers the advantages of (a) low-voltage implementation, (b) integrablity as the design is resistor- and inductor-less and only grounded components have been employed in the design, and, (c) electronic tunability of the fractional order, time-constants and gain factors. In order to demonstrate the usefulness of the chaotic system, a simple secure message communication system has been designed and verified for its operation. The theoretical predictions of the proposed implementations have been verified by using 0.35[Formula: see text][Formula: see text]m complementary metal oxide semiconductor (CMOS) process file provided by Austrian Micro System (AMS).

A TIME-DOMAIN 1.0-V/0.8-MW 6-BIT 125 MS/S FLASH ADC IN 65 NM CMOS

2013 ◽  
Vol 22 (04) ◽  
pp. 1350017 ◽  
Author(s):  
GUANZHONG HUANG ◽  
PINGFEN LIN
Keyword(s):  
Time Domain ◽  
Pulse Width Modulation ◽  
Low Voltage ◽  
Sampling Rate ◽  
Digital Signal ◽  
Input Voltage ◽  
Gray Code ◽  
Digital Circuit ◽  
Cmos Process ◽  
Flash Adc

A 6-bit low-voltage power-efficient flash analog-to-digital converter (ADC) is presented in this paper. The proposed ADC replaces the conventional voltage comparator with a new approach in the time-domain. The reference voltages and the analog input voltage are converted to digital signal in a form of different pulse widths by using a pulse-width-modulation (PWM) circuit. Consequently, the comparison is achieved by checking the sequence of the pulse rising edges rather than amplifying and latching the voltage difference. The total input capacitance of the proposed ADC is as small as tens of femto-farads, resulting in much less demand for the front-end buffer and the sampling switch. In addition, an implementation of the digital foreground calibration helps to get rid of the nonmonotonic comparison thresholds due to mismatch. The calibration operates with the adaptive comparison threshold by tuning the modulation level of the PWM. The intermediate Gray code conversion increases the bubble tolerance by 1LSB. This digital-circuit-heavily-involved ADC has been designed and simulated in a 65 nm CMOS process, achieving 35.24 dB signal-to-noise-and-distortion-ratio (SNDR) at a sampling rate of 125 MS/s while consuming 803 μW from 1 V power supply. As a result, the figure of merit (FoM) is as low as 136 fJ/conversion-step.

scholarly journals A Highly Linear CMOS Image Sensor Design Based on an Adaptive Nonlinear Ramp Generator and Fully Differential Pipeline Sampling Quantization with a Double Auto-Zeroing Technique

Sensors ◽  
2020 ◽  
Vol 20 (4) ◽  
pp. 1046
Author(s):  
Chuangze Li ◽  
Benguang Han ◽  
Jie He ◽  
Zhongjie Guo ◽  
Longsheng Wu
Keyword(s):  
Complementary Metal Oxide Semiconductor ◽  
Cmos Image Sensor ◽  
Image Sensor ◽  
Frame Rate ◽  
Oxide Semiconductor ◽  
Ramp Generator ◽  
Fully Differential ◽  
Generator Circuit ◽  
Pattern Noise ◽  
Fixed Pattern Noise

For a complementary metal-oxide-semiconductor image sensor with highly linear, low noise and high frame rate, the nonlinear correction and frame rate improvement techniques are becoming very important. The in-pixel source follower transistor and the integration capacitor on the floating diffusion node cause linearity degradation. In order to address this problem, this paper proposes an adaptive nonlinear ramp generator circuit based on dummy pixels used in single-slope analog-to-digital converter topology for a complementary metal-oxide-semiconductor (CMOS) image sensor. In the proposed approach, the traditional linear ramp generator circuit is replaced with the new proposed adaptive nonlinear ramp generator circuit that can mitigate the nonlinearity of the pixel unit circuit, especially the gain nonlinearity of the source follower transistor and the integration capacitor nonlinearity of the floating diffusion node. Moreover, in order to enhance the frame rate and address the issue of high column fixed pattern noise, a new readout scheme of fully differential pipeline sampling quantization with a double auto-zeroing technique is proposed. Compared with the conventional readout structure without a fully differential pipeline sampling quantization technique and double auto-zeroing technique, the proposed readout scheme cannot only enhance the frame rate but can also improve the consistency of the offset and delay information of different column comparators and significantly reduce the column fixed pattern noise. The proposed techniques are simulated and verified with a prototype chip fabricated using typical 180 nm CMOS process technology. The obtained measurement results demonstrate that the overall nonlinearity of the CMOS image sensor is reduced from 1.03% to 0.047%, the efficiency of the comparator is improved from 85.3% to 100%, and the column fixed pattern noise is reduced from 0.43% to 0.019%.

scholarly journals Low-Voltage Complex Filters Using Current Feedback Operational Amplifiers

2013 ◽  
Vol 2013 ◽  
pp. 1-7 ◽  
Author(s):  
Panagiotis Samiotis ◽  
Costas Psychalinos
Keyword(s):  
Low Voltage ◽  
Operational Amplifiers ◽  
Cmos Process ◽  
Current Feedback ◽  
Mos Transistor ◽  
Low Voltage Operation ◽  
Current Feedback Operational Amplifiers ◽  
Novel Complex ◽  
Simulation Results ◽  
Frequency Behavior

A novel complex filter topology realized using current feedback operational amplifiers as active elements is introduced in this paper. Offered benefits are the low-voltage operation capability and the requirement for employing only grounded passive elements. Two application examples are provided, where the frequency behavior of the derived filters fulfills the ZigBee and Bluetooth standards, respectively. Their performance evaluation has been done through simulation results at postlayout level, using MOS transistor models provided by AMS C35B4 CMOS process.

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