scholarly journals Novel 9-Steps Automatic AC Voltage Regulator based on Two Step-down Transformers

2017 ◽  
Vol 7 (2) ◽  
pp. 576
Author(s):  
Hussain Attia
Keyword(s):  
Circuit Design ◽  
Supply Voltage ◽  
Electrical Circuit ◽  
Voltage Regulator ◽  
Voltage Step ◽  
Power Circuit ◽  
One Step ◽  
Simulation Results ◽  
Step Down ◽  
Novel Design

<p class="IEEEAbtract">A novel design and simulation results of 9-steps automatic AC voltage regulator based on one step-down transformer is presented in this paper. Avoiding the problem of surge at the AC load during controlling jump steps is done through the proposed design. Accurate and smooth controlling function is achieved as well. Instead of the necessity of increasing the number of taps of the used multi tap transformer for wide controlling range of fluctuated AC  supply voltage, the proposed designed adopts using only two step down transformers with 10 Vrms, and 30 Vrms secondary voltages respectively. Through the controlling of the proposed design of AV voltage regulator, the resultant load voltage is equal the AC supply voltage as well as the suitable voltage step which may one of the following voltages; +40V, +30V, +20V, +10V, 0V, -10V, -20V, -30V, -40V. The electronic design is done Multisim software while the electrical circuit connection of step down transformers and relays contacts that is made by using PSIM software for power circuit design.</p>

A Novel CNFET Technology Based 3 Bit Flash ADC for Low-Voltage High Speed SoC Application

2015 ◽  
Vol 19 ◽  
pp. 19-36 ◽  
Author(s):  
P.A. Gowri Sankar ◽  
G. Sathiyabama
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Circuit Design ◽  
Field Effect ◽  
High Speed ◽  
Low Voltage ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Flash Adc ◽  
Simulation Results

The continuous scaling down of metal-oxide-semiconductor field effect transistors (MOSFETs) led to the considerable impact in the analog-digital mixed signal integrated circuit design for system-on-chips (SoCs) application. SoCs trends force ADCs to be integrated on the chip with other digital circuits. These trends present new challenges in ADC circuit design based on existing CMOS technology. In this paper, we have designed and analyzed a 3-bit high speed, low-voltage and low-power flash ADC at 32nm CNFET technology for SoC applications. The proposed ADC utilizes the Threshold Inverter Quantization (TIQ) technique that uses two cascaded carbon nanotube field effect transistor (CNFET) inverters as a comparator. The TIQ technique proposed has been developed for better implementation in SoC applications. The performance of the proposed ADC is studied using two different types of encoders such as ROM and Fat tree encoders. The proposed ADCs circuits are simulated using Synopsys HSPICE with standard 32nm CNFET model at 0.9 input supply voltage. The simulation results show that the proposed 3 bit TIQ technique based flash ADC with fat tree encoder operates up to 8 giga samples per second (GSPS) with 35.88µW power consumption. From the simulation results, we observed that the proposed TIQ flash ADC achieves high speed, small size, low power consumption, and low voltage operation compared to other low power CMOS technology based flash ADCs. The proposed method is sensitive to process, temperature and power supply voltage variations and their impact on the ADC performance is also investigated.

Design of a Sawtooth Generator Applied for Class-D Audio Power Amplifier

2012 ◽  
Vol 241-244 ◽  
pp. 693-697
Author(s):  
Zi Yi Liu ◽  
Xing Xing Jing ◽  
Wen Xi
Keyword(s):  
Circuit Design ◽  
Power Amplifier ◽  
Pulse Width ◽  
Pulse Width Modulation ◽  
Voltage Regulator ◽  
Core Component ◽  
Audio Amplifier ◽  
Class D ◽  
Simulation Results ◽  
Sawtooth Generator

A systematic introduction to principles and advantages of the class-D audio amplifier based on pulse width modulation (PWM) are presented in this paper. The traditional sawtooth generator needs voltage-regulator tube to server as a core component. Against to such a disadvantage a simple way based on the charging and discharging capacitance is proposed to achieve sawtooth generator. The circuit design is based on SIMC 0.18um process. Spectre simulation results show that the sawtooth generator's performance is good. And it suits for the design of class-D audio power amplifier chip.

scholarly journals A Novel Cross-Latch Shift Register Scheme for Low Power Applications

2020 ◽  
Vol 11 (1) ◽  
pp. 129
Author(s):  
Po-Yu Kuo ◽  
Ming-Hwa Sheu ◽  
Chang-Ming Tsai ◽  
Ming-Yan Tsai ◽  
Jin-Fa Lin
Keyword(s):  
Power Consumption ◽  
Supply Voltage ◽  
Electrical Power ◽  
Average Power ◽  
Leakage Power ◽  
Shift Register ◽  
Cmos Process ◽  
Average Power Consumption ◽  
Simulation Results ◽  
Layout Area

The conventional shift register consists of master and slave (MS) latches with each latch receiving the data from the previous stage. Therefore, the same data are stored in two latches separately. It leads to consuming more electrical power and occupying more layout area, which is not satisfactory to most circuit designers. To solve this issue, a novel cross-latch shift register (CLSR) scheme is proposed. It significantly reduced the number of transistors needed for a 256-bit shifter register by 48.33% as compared with the conventional MS latch design. To further verify its functions, this CLSR was implemented by using TSMC 40 nm CMOS process standard technology. The simulation results reveal that the proposed CLSR reduced the average power consumption by 36%, cut the leakage power by 60.53%, and eliminated layout area by 34.76% at a supply voltage of 0.9 V with an operating frequency of 250 MHz, as compared with the MS latch.

Sine-cosine algorithm-based optimization for automatic voltage regulator system

2018 ◽  
Vol 41 (6) ◽  
pp. 1761-1771 ◽  
Author(s):  
Baran Hekimoğlu
Keyword(s):  
Pid Controller ◽  
Design Method ◽  
Voltage Regulator ◽  
Bee Colony ◽  
Automatic Voltage Regulator ◽  
Avr System ◽  
Sine Cosine Algorithm ◽  
Tuning Methods ◽  
Domain Performance ◽  
Novel Design

A novel design method, sine-cosine algorithm (SCA) is presented in this paper to determine optimum proportional-integral-derivative (PID) controller parameters of an automatic voltage regulator (AVR) system. The proposed approach is a simple yet effective algorithm that has balanced exploration and exploitation capabilities to search the solutions space effectively to find the best result. The simplicity of the algorithm provides fast and high-quality tuning of optimum PID controller parameters. The proposed SCA-PID controller is validated by using a time domain performance index. The proposed method was found efficient and robust in improving the transient response of AVR system compared with the PID controllers based on Ziegler-Nichols (ZN), differential evolution (DE), artificial bee colony (ABC) and bio-geography-based optimization (BBO) tuning methods.

Simulation and Research of Dynamic Voltage Detection and Regulator Based on MATLAB

2014 ◽  
Vol 536-537 ◽  
pp. 1527-1531
Author(s):  
Ya Feng Li ◽  
Zi Wei Zheng
Keyword(s):  
Theoretical Analysis ◽  
Reactive Power ◽  
Voltage Regulator ◽  
New Approach ◽  
Dynamic Voltage ◽  
Harmonic Voltage ◽  
Simulation Results ◽  
Harmonic Source ◽  
Detecting Method ◽  
Dynamic Voltage Regulator

The Series Dynamic Voltage Regulator can compensate the harmonics distortion caused by voltage type harmonic source This paper presents a new approach of detecting harmonic voltage in dq0 coordinates, based on the generalized instantaneous reactive power ,and used in the series dynamic voltage regulator successfully. It is demonstrated by theoretical analysis and simulation results that the proposed detecting method of harmonic voltage is correct and valid.

scholarly journals The multilevel inverter with clamped-diode

2019 ◽  
Vol 14 (3) ◽  
pp. 1189
Author(s):  
Trong-Thang Nguyen
Keyword(s):  
Numerical Simulation ◽  
Circuit Design ◽  
Output Voltage ◽  
Harmonic Distortion ◽  
Control Circuit ◽  
Multilevel Inverter ◽  
Power Circuit ◽  
Advantages And Disadvantages ◽  
Multi Level ◽  
And Control

<p>In this study, the author analyzes the advantages and disadvantages of multi-level inverter compared to the traditional two-level inverter and then chose the suitable inverter. Specifically, the author analyzes and designs the three-level inverter, including the power circuit design and control circuit design. All designs are verified through the numerical simulation on Matlab. The results show that even though the three-level inverter has a low number of switches (only 12 switches), but the quality is very good: the total harmonic distortion is small; the output voltage always follows the reference voltage.</p>

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