scholarly journals Optimal design of CMOS current mode instrumentation amplifier using bio-inspired method for biomedical applications

2022 ◽  
Vol 25 (1) ◽  
pp. 120
Author(s):  
Issa Sabiri ◽  
Hamid Bouyghf ◽  
Abdelhadi Raihani ◽  
Brahim Ouacha
Keyword(s):  
Integrated Circuits ◽  
Biomedical Applications ◽  
Complementary Metal Oxide Semiconductor ◽  
Current Mode ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Design System ◽  
Instrumentation Amplifier ◽  
Large Bandwidth ◽  
Bee Colony

Analog integrated circuits for biomedical applications require good performance. This paper presents an instrumentation amplifier (IA) design based on three complementary metal oxide semiconductor (CMOS) conveyors with an active resistor. This circuit offers the possibility to control the gain by voltage and current. We have designed the IA to minimize the parasitic resistance (Rx) with large bandwidth and high common mode rejection ratio (CMRR) using the artificial bee colony algorithm (ABC). The topology is simulated using 0.35µm CMOS technology parameters. The optimization problem is represented by an objective function that will be implemented using MATLAB script. The results were approved by the simulation using the advanced design system (ADS) tool. The simulation results were compared to the characteristics of some other instrumentation amplifiers exsisting in the literature. The circuit has a higher CMRR than other topologies.

scholarly journals Investigation of PVT-Aware STT-MRAM Sensing Circuits for Low-VDD Scenario

Micromachines ◽  
2021 ◽  
Vol 12 (5) ◽  
pp. 551
Author(s):  
Zhongjian Bian ◽  
Xiaofeng Hong ◽  
Yanan Guo ◽  
Lirida Naviner ◽  
Wei Ge ◽  
...  
Keyword(s):  
Nonvolatile Memory ◽  
High Speed ◽  
Low Voltage ◽  
Supply Voltage ◽  
Random Access ◽  
Magnetic Tunnel Junction ◽  
Complementary Metal Oxide Semiconductor ◽  
Current Mode ◽  
Cmos Technology ◽  
Oxide Semiconductor

Spintronic based embedded magnetic random access memory (eMRAM) is becoming a foundry validated solution for the next-generation nonvolatile memory applications. The hybrid complementary metal-oxide-semiconductor (CMOS)/magnetic tunnel junction (MTJ) integration has been selected as a proper candidate for energy harvesting, area-constraint and energy-efficiency Internet of Things (IoT) systems-on-chips. Multi-VDD (low supply voltage) techniques were adopted to minimize energy dissipation in MRAM, at the cost of reduced writing/sensing speed and margin. Meanwhile, yield can be severely affected due to variations in process parameters. In this work, we conduct a thorough analysis of MRAM sensing margin and yield. We propose a current-mode sensing amplifier (CSA) named 1D high-sensing 1D margin, high 1D speed and 1D stability (HMSS-SA) with reconfigured reference path and pre-charge transistor. Process-voltage-temperature (PVT) aware analysis is performed based on an MTJ compact model and an industrial 28 nm CMOS technology, explicitly considering low-voltage (0.7 V), low tunneling magnetoresistance (TMR) (50%) and high temperature (85 °C) scenario as the worst sensing case. A case study takes a brief look at sensing circuits, which is applied to in-memory bit-wise computing. Simulation results indicate that the proposed high-sensing margin, high speed and stability sensing-sensing amplifier (HMSS-SA) achieves remarkable performance up to 2.5 GHz sensing frequency. At 0.65 V supply voltage, it can achieve 1 GHz operation frequency with only 0.3% failure rate.

scholarly journals New Radiation-Hardened Design of a CMOS Instrumentation Amplifier and its Tolerant Characteristic Analysis

Electronics ◽  
2020 ◽  
Vol 9 (3) ◽  
pp. 388 ◽  
Author(s):  
Minwoong Lee ◽  
Seongik Cho ◽  
Namho Lee ◽  
Jongyeol Kim
Keyword(s):  
Integrated Circuits ◽  
Nuclear Power ◽  
Power Plants ◽  
Complementary Metal Oxide Semiconductor ◽  
Low Power Design ◽  
Oxide Semiconductor ◽  
Instrumentation Amplifier ◽  
Negative Effects ◽  
Characteristic Analysis ◽  
Radiation Hardened

A radiation-hardened instrumentation amplifier (IA) that allows precise measurement in radiation environments, including nuclear power plants, space environments, and radiation therapy rooms, was designed and manufactured, and its characteristics were verified. Most electronic systems are currently designed using silicon-based complementary metal-oxide semiconductor (CMOS) integrated circuits (ICs) to achieve a highly integrated low-power design. However, fixed charges induced in silicon by ionization radiation cause various negative effects, resulting in, for example, the generation of leakage current in circuits, performance degradation, and malfunction. Given that such problems in radiation environments may directly lead to a loss of life or environmental contamination, it is critical to implement radiation-hardened CMOS IC technology. In this study, an IA used to amplify fine signals of the sensors was designed and fabricated in the 0.18 μm CMOS bulk process. The IA contained sub-circuits that ensured the stable voltage supply needed to implement system-on-chip (SoC) solutions. It was also equipped with special radiation-hardening technology by applying an I-gate n-MOSFET that blocks the radiation-induced leakage currents. Its ICs were verified to provide the intended performance following a total cumulative dose of up to 25 kGy(Si), ensuring its safety in radiation environments.

scholarly journals An Analogue Multiplier using CNTFET Technology

2020 ◽  
Vol 19 ◽  
Keyword(s):  
Analog Circuits ◽  
Supply Voltage ◽  
Complementary Metal Oxide Semiconductor ◽  
Current Mode ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Analog Multiplier ◽  
Effect Transistor ◽  
Four Quadrant ◽  
Better Than

The endeavor to overcome problems of complementary metal oxide semiconductor technology makes the advent of Carbon nanotube field effect transistor (CNTFET). Improvement of structure transistor CNTFET makes higher mobility and electrostatics of gate electrons. Therefore, many analog circuits are now designed based on CNTFET technology. This paper presents a low power current mode four-quadrant analog multiplier based on CNTFET and CMOS technologies. All simulations were done with the synopsys Hspice simulator using 32nm CNTFET model from Stanford University and 32nm CMOS from PTM library at a supply voltage of 3.3 v. It was shown that the simulation of a multiplier based on CNTFET technology performs better than a multiplier based on CMOS technology.

scholarly journals Optimal Physical Implementation of Radiation Tolerant High-Speed Digital Integrated Circuits in Deep-Submicron Technologies

Electronics ◽  
2019 ◽  
Vol 8 (4) ◽  
pp. 432 ◽  
Author(s):  
Jeffrey Prinzie ◽  
Karel Appels ◽  
Szymon Kulis
Keyword(s):  
Integrated Circuits ◽  
High Speed ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Deep Submicron ◽  
Oxide Semiconductor ◽  
Digital Integrated Circuits ◽  
Physical Implementation ◽  
Radiation Hard ◽  
Radiation Tolerant

This paper presents a novel scalable physical implementation method for high-speed Triple Modular Redundant (TMR) digital integrated circuits in radiation-hard designs. The implementation uses a distributed placement strategy compared to a commonly used bulk 3-bank constraining method. TMR netlist information is used to optimally constrain the placement of both sequential cells and combinational cells. This approach significantly reduces routing complexity, net lengths and dynamic power consumption with more than 60% and 20% respectively. The technique was simulated in a 65 nm Complementary Metal-Oxide Semiconductor (CMOS) technology.

scholarly journals Excel Methods to Design and Validate in Microelectronics (Complementary Metal–Oxide–Semiconductor, CMOS) for Biomedical Instrumentation Application

Sensors ◽  
2021 ◽  
Vol 21 (22) ◽  
pp. 7486
Author(s):  
Graciano Dieck-Assad ◽  
José Manuel Rodríguez-Delgado ◽  
Omar Israel González Peña
Keyword(s):  
Integrated Circuits ◽  
Degrees Of Freedom ◽  
Low Voltage ◽  
Complementary Metal Oxide Semiconductor ◽  
Open Science ◽  
Oxide Semiconductor ◽  
Instrumentation Amplifier ◽  
Short Channel ◽  
Transconductance Amplifier ◽  
Cmos Mems

CMOS microelectronics design has evolved tremendously during the last two decades. The evolution of CMOS devices to short channel designs where the feature size is below 1000 nm brings a great deal of uncertainty in the way the microelectronics design cycle is completed. After the conceptual idea, developing a thinking model to understand the operation of the device requires a good “ballpark” evaluation of transistor sizes, decision making, and assumptions to fulfill the specifications. This design process has iterations to meet specifications that exceed in number of the available degrees of freedom to maneuver the design. Once the thinking model is developed, the simulation validation follows to test if the design has a good possibility of delivering a successful prototype. If the simulation provides a good match between specifications and results, then the layout is developed. This paper shows a useful open science strategy, using the Excel software, to develop CMOS microelectronics hand calculations to verify a design, before performing the computer simulation and layout of CMOS analog integrated circuits. The full methodology is described to develop designs of passive components, as well as CMOS amplifiers. The methods are used in teaching CMOS microelectronics to students of electronic engineering with industrial partner participation. This paper describes an exhaustive example of a low-voltage operational transconductance amplifier (OTA) design which is used to design an instrumentation amplifier. Finally, a test is performed using this instrumentation amplifier to implement a front-end signal conditioning device for CMOS-MEMS biomedical applications.

A 32-Gb/s On-Chip Bus With Driver Pre-Emphasis Signaling

2009 ◽  
Vol 17 (9) ◽  
pp. 1267-1274 ◽  
Author(s):  
Liang Zhang ◽  
John M. Wilson ◽  
Rizwan Bashirullah ◽  
Lei Luo ◽  
Jian Xu ◽  
...  
Keyword(s):  
Power Dissipation ◽  
Complementary Metal Oxide Semiconductor ◽  
Current Mode ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Signal Delay ◽  
Crosstalk Noise ◽  
High Data ◽  
On Chip ◽  
Bus Architecture

This paper describes a differential current-mode bus architecture based on driver pre-emphasis for on-chip global interconnects that achieves high-data rates while reducing bus power dissipation and improving signal delay latency. The 16-b bus core fabricated in 0.25-mum complementary metal-oxide-semiconductor (CMOS) technology attains an aggregate signaling data rate of 32 Gb/s over 5-10-mm-long lossy interconnects. With a supply of 2.5 V, 25.5-48.7-mW power dissipation was measured for signal activity above 0.1, equivalent to 0.80-1.52 pJ/b. This work demonstrates a 15.0%-67.5% power reduction over a conventional single-ended voltage-mode static bus while reducing delay latency by 28.3% and peak current by 70%. The proposed bus architecture is robust against crosstalk noise and occupies comparable routing area to a reference static bus design.

scholarly journals Towards Fully Integrated Portable Sensing Devices for COVID-19 and Future Global Hazards: Recent Advances, Challenges, and Prospects

Micromachines ◽  
2021 ◽  
Vol 12 (8) ◽  
pp. 915
Author(s):  
Tina Shaffaf ◽  
Saghi Forouhi ◽  
Ebrahim Ghafar-Zadeh
Keyword(s):  
Integrated Circuits ◽  
Point Of Care ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Turnaround Time ◽  
Oxide Semiconductor ◽  
Time Duration ◽  
Fully Integrated ◽  
Diagnostic Assays ◽  
Hands On

Since the onset of the coronavirus disease 2019 (COVID-19) pandemic, this fatal disease has been the leading cause of the death of more than 3.9 million people around the world. This tragedy taught us that we should be well-prepared to control the spread of such infectious diseases and prevent future hazards. As a consequence, this pandemic has drawn the attention of many researchers to the development of portable platforms with short hands-on and turnaround time suitable for batch production in urgent pandemic situations such as that of COVID-19. Two main groups of diagnostic assays have been reported for the detection of Severe Acute Respiratory Syndrome Coronavirus 2 (SARS-CoV-2) including nucleic acid-based and protein-based assays. The main focus of this paper is on the latter, which requires a shorter time duration, less skilled technicians, and faces lower contamination. Furthermore, this paper gives an overview of the complementary metal-oxide-semiconductor (CMOS) biosensors, which are potentially useful for implementing point-of-care (PoC) platforms based on such assays. CMOS technology, as a predominant technology for the fabrication of integrated circuits, is a promising candidate for the development of PoC devices by offering the advantages of reliability, accessibility, scalability, low power consumption, and distinct cost.

Computational study of the staircase molecular conductivity of polyoxovanadates adsorbed on Au(111)

2021 ◽  
Vol 50 (16) ◽  
pp. 5540-5551
Author(s):  
Almudena Notario-Estévez ◽  
Xavier López ◽  
Coen de Graaf
Keyword(s):  
Metal Oxide ◽  
Computational Study ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Molecular Conduction ◽  
Conduction Properties ◽  
Molecular Conductivity

This computational study presents the molecular conduction properties of polyoxovanadates V6O19 (Lindqvist-type) and V18O42, as possible successors of the materials currently in use in complementary metal–oxide semiconductor (CMOS) technology.

Deep-Submicron Single-Gate Complementary Metal Oxide Semiconductor (CMOS) Technology Using Channel Preamorphization

1998 ◽  
Vol 37 (Part 1, No. 3B) ◽  
pp. 1050-1053 ◽  
Author(s):  
Masayasu Miyake ◽  
Toshio Kobayashi ◽  
Yutaka Sakakibara ◽  
Kimiyoshi Deguchi ◽  
Mitsutoshi Takahashi
Keyword(s):  
Metal Oxide ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Deep Submicron ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor

A 60 GHz reconfigurable active phase shifter based on a vector modulator in 65 nm CMOS technology

2016 ◽  
Vol 8 (3) ◽  
pp. 399-404 ◽  
Author(s):  
Boris Moret ◽  
Nathalie Deltimple ◽  
Eric Kerhervé ◽  
Baudouin Martineau ◽  
Didier Belot
Keyword(s):  
Phase Shift ◽  
Phase Shifter ◽  
Complementary Metal Oxide Semiconductor ◽  
Active Phase ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
60 Ghz ◽  
Semiconductor Technology ◽  
Vector Modulator ◽  
Active Phase Shifter

This paper presents a 60 GHz reconfigurable active phase shifter based on a vector modulator implemented in 65 nm complementary metal–oxide–semiconductor technology. This circuit is based on the recombination of two differential paths in quadrature. The proposed vector modulator allows us to generate a phase shift between 0° and 360°. The voltage gain varies between −13 and −9 dB in function of the phase shift generated with a static consumption between 26 and 63 mW depending on its configuration.

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