scholarly journals New Radiation-Hardened Design of a CMOS Instrumentation Amplifier and its Tolerant Characteristic Analysis

Electronics ◽  
2020 ◽  
Vol 9 (3) ◽  
pp. 388 ◽  
Author(s):  
Minwoong Lee ◽  
Seongik Cho ◽  
Namho Lee ◽  
Jongyeol Kim
Keyword(s):  
Integrated Circuits ◽  
Nuclear Power ◽  
Power Plants ◽  
Complementary Metal Oxide Semiconductor ◽  
Low Power Design ◽  
Oxide Semiconductor ◽  
Instrumentation Amplifier ◽  
Negative Effects ◽  
Characteristic Analysis ◽  
Radiation Hardened

A radiation-hardened instrumentation amplifier (IA) that allows precise measurement in radiation environments, including nuclear power plants, space environments, and radiation therapy rooms, was designed and manufactured, and its characteristics were verified. Most electronic systems are currently designed using silicon-based complementary metal-oxide semiconductor (CMOS) integrated circuits (ICs) to achieve a highly integrated low-power design. However, fixed charges induced in silicon by ionization radiation cause various negative effects, resulting in, for example, the generation of leakage current in circuits, performance degradation, and malfunction. Given that such problems in radiation environments may directly lead to a loss of life or environmental contamination, it is critical to implement radiation-hardened CMOS IC technology. In this study, an IA used to amplify fine signals of the sensors was designed and fabricated in the 0.18 μm CMOS bulk process. The IA contained sub-circuits that ensured the stable voltage supply needed to implement system-on-chip (SoC) solutions. It was also equipped with special radiation-hardening technology by applying an I-gate n-MOSFET that blocks the radiation-induced leakage currents. Its ICs were verified to provide the intended performance following a total cumulative dose of up to 25 kGy(Si), ensuring its safety in radiation environments.

scholarly journals Optimal design of CMOS current mode instrumentation amplifier using bio-inspired method for biomedical applications

2022 ◽  
Vol 25 (1) ◽  
pp. 120
Author(s):  
Issa Sabiri ◽  
Hamid Bouyghf ◽  
Abdelhadi Raihani ◽  
Brahim Ouacha
Keyword(s):  
Integrated Circuits ◽  
Biomedical Applications ◽  
Complementary Metal Oxide Semiconductor ◽  
Current Mode ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Design System ◽  
Instrumentation Amplifier ◽  
Large Bandwidth ◽  
Bee Colony

Analog integrated circuits for biomedical applications require good performance. This paper presents an instrumentation amplifier (IA) design based on three complementary metal oxide semiconductor (CMOS) conveyors with an active resistor. This circuit offers the possibility to control the gain by voltage and current. We have designed the IA to minimize the parasitic resistance (Rx) with large bandwidth and high common mode rejection ratio (CMRR) using the artificial bee colony algorithm (ABC). The topology is simulated using 0.35µm CMOS technology parameters. The optimization problem is represented by an objective function that will be implemented using MATLAB script. The results were approved by the simulation using the advanced design system (ADS) tool. The simulation results were compared to the characteristics of some other instrumentation amplifiers exsisting in the literature. The circuit has a higher CMRR than other topologies.

Minimization of Leakage Currents in Dram 4x4 Using SVL Technique

2021 ◽  
pp. 221-228
Author(s):  
N. Geetha Rani ◽  
C. Soundarya Lahari ◽  
G. Revathi ◽  
K. Chandrika ◽  
G. Riya
Keyword(s):  
Integrated Circuits ◽  
Low Power ◽  
Integrated Circuit ◽  
Heat Dissipation ◽  
Average Power ◽  
Complementary Metal Oxide Semiconductor ◽  
Low Power Design ◽  
Oxide Semiconductor ◽  
Portable Devices ◽  
Leakage Currents

In recent years, due to development of integrated circuits technology, power is being given comparable weight to area and speed considerations. The power consumed for any given function in any complementary metal-oxide-semiconductor (CMOS) circuit must be reduced for either of the two different reasons. One is to reduce heat dissipation in order to allow a large density of functions to be incorporated on an Integrated Circuit (IC) chip. Any amount of power dissipation is worthwhile as long as it does not degrade overall circuit performance. The other reason is to save energy in battery operated instruments like in electronic watches where average power is in microwatts. Low power is the major issue not only in portable devices but also in non-portable devices. So, it is apparent that one has to resolve low power design methodologies for the design of high throughput, low power digital systems. By using this SVL technique using DRAM we are going to reduce the leakage currents and also improves the performance of the circuit.

scholarly journals Excel Methods to Design and Validate in Microelectronics (Complementary Metal–Oxide–Semiconductor, CMOS) for Biomedical Instrumentation Application

Sensors ◽  
2021 ◽  
Vol 21 (22) ◽  
pp. 7486
Author(s):  
Graciano Dieck-Assad ◽  
José Manuel Rodríguez-Delgado ◽  
Omar Israel González Peña
Keyword(s):  
Integrated Circuits ◽  
Degrees Of Freedom ◽  
Low Voltage ◽  
Complementary Metal Oxide Semiconductor ◽  
Open Science ◽  
Oxide Semiconductor ◽  
Instrumentation Amplifier ◽  
Short Channel ◽  
Transconductance Amplifier ◽  
Cmos Mems

CMOS microelectronics design has evolved tremendously during the last two decades. The evolution of CMOS devices to short channel designs where the feature size is below 1000 nm brings a great deal of uncertainty in the way the microelectronics design cycle is completed. After the conceptual idea, developing a thinking model to understand the operation of the device requires a good “ballpark” evaluation of transistor sizes, decision making, and assumptions to fulfill the specifications. This design process has iterations to meet specifications that exceed in number of the available degrees of freedom to maneuver the design. Once the thinking model is developed, the simulation validation follows to test if the design has a good possibility of delivering a successful prototype. If the simulation provides a good match between specifications and results, then the layout is developed. This paper shows a useful open science strategy, using the Excel software, to develop CMOS microelectronics hand calculations to verify a design, before performing the computer simulation and layout of CMOS analog integrated circuits. The full methodology is described to develop designs of passive components, as well as CMOS amplifiers. The methods are used in teaching CMOS microelectronics to students of electronic engineering with industrial partner participation. This paper describes an exhaustive example of a low-voltage operational transconductance amplifier (OTA) design which is used to design an instrumentation amplifier. Finally, a test is performed using this instrumentation amplifier to implement a front-end signal conditioning device for CMOS-MEMS biomedical applications.

scholarly journals A Radiation-Hardened Instrumentation Amplifier for Sensor Readout Integrated Circuits in Nuclear Fusion Applications

Electronics ◽  
2018 ◽  
Vol 7 (12) ◽  
pp. 429 ◽  
Author(s):  
Kyungsoo Jeong ◽  
Duckhoon Ro ◽  
Gwanho Lee ◽  
Myounggon Kang ◽  
Hyung-Min Lee
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
Radiation Effects ◽  
Nuclear Fusion ◽  
Oxide Semiconductor ◽  
Instrumentation Amplifier ◽  
Cmos Process ◽  
Readout Integrated Circuit ◽  
Nuclear Fusion Reactor ◽  
Radiation Hardened

A nuclear fusion reactor requires a radiation-hardened sensor readout integrated circuit (IC), whose operation should be tolerant against harsh radiation effects up to MGy or higher. This paper proposes radiation-hardening circuit design techniques for an instrumentation amplifier (IA), which is one of the most sensitive circuits in the sensor readout IC. The paper studied design considerations for choosing the IA topology for radiation environments and proposes a radiation-hardened IA structure with total-ionizing-dose (TID) effect monitoring and adaptive reference control functions. The radiation-hardened performance of the proposed IA was verified through model-based circuit simulations by using compact transistor models that reflected the TID effects into complementary metal–oxide–semiconductor (CMOS) parameters. The proposed IA was designed with the 65 nm standard CMOS process and provides adjustable voltage gain between 3 and 15, bandwidth up to 400 kHz, and power consumption of 34.6 μW, while maintaining a stable performance over TID effects up to 1 MGy.

Operating Reliability Assessment of FPGA-Based NPP I&C Systems: Approach, Technique and Implementation

2017 ◽  
Author(s):  
Eugene Babeshko ◽  
Ievgenii Bakhmach ◽  
Vyacheslav Kharchenko ◽  
Eugene Ruchkov ◽  
Oleksandr Siora
Keyword(s):  
Integrated Circuits ◽  
Nuclear Power ◽  
Power Plants ◽  
Failure Modes ◽  
New Technologies ◽  
Systems Approach ◽  
Reliability Assessment ◽  
Design Stage ◽  
Fpga Design ◽  
Operating Reliability

Operating reliability assessment of instrumentation and control systems (I&Cs) is always one of the most important activities, especially for critical domains like nuclear power plants (NPPs). Intensive use of relatively new technologies like field programmable gate arrays (FPGAs) in I&C which appear in upgrades and in newly built NPPs makes task to develop and validate advanced operating reliability assessment methods that consider specific technology features very topical. Increased integration densities make the reliability of integrated circuits the most crucial point in modern NPP I&Cs. Moreover, FPGAs differ in some significant ways from other integrated circuits: they are shipped as blanks and are very dependent on design configured into them. Furthermore, FPGA design could be changed during planned NPP outage for different reasons. Considering all possible failure modes of FPGA-based NPP I&C at design stage is a quite challenging task. Therefore, operating reliability assessment is one of the most preferable ways to perform comprehensive analysis of FPGA-based NPP I&Cs. This paper summarizes our experience on operating reliability analysis of FPGA based NPP I&Cs.

scholarly journals Low Power Robust Early Output Asynchronous Block Carry Lookahead Adder with Redundant Carry Logic

Electronics ◽  
2018 ◽  
Vol 7 (10) ◽  
pp. 243 ◽  
Author(s):  
Padmanabhan Balasubramanian ◽  
Douglas Maskell ◽  
Nikos Mastorakis
Keyword(s):  
Low Power ◽  
Digital Signal Processor ◽  
Digital Signal ◽  
Complementary Metal Oxide Semiconductor ◽  
Low Power Design ◽  
Cmos Technology ◽  
General Purpose ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Power Cycle

Adder is an important datapath unit of a general-purpose microprocessor or a digital signal processor. In the nanoelectronics era, the design of an adder that is modular and which can withstand variations in process, voltage and temperature are of interest. In this context, this article presents a new robust early output asynchronous block carry lookahead adder (BCLA) with redundant carry logic (BCLARC) that has a reduced power-cycle time product (PCTP) and is a low power design. The proposed asynchronous BCLARC is implemented using the delay-insensitive dual-rail code and adheres to the 4-phase return-to-zero (RTZ) and the 4-phase return-to-one (RTO) handshaking. Many existing asynchronous ripple-carry adders (RCAs), carry lookahead adders (CLAs) and carry select adders (CSLAs) were implemented alongside to perform a comparison based on a 32/28 nm complementary metal-oxide-semiconductor (CMOS) technology. The 32-bit addition was considered for an example. For implementation using the delay-insensitive dual-rail code and subject to the 4-phase RTZ handshaking (4-phase RTO handshaking), the proposed BCLARC which is robust and of early output type achieves: (i) 8% (5.7%) reduction in PCTP compared to the optimum RCA, (ii) 14.9% (15.5%) reduction in PCTP compared to the optimum BCLARC, and (iii) 26% (25.5%) reduction in PCTP compared to the optimum CSLA.

Analysis and Simulation of a Low-Leakage Analog Single Gate and FinFET Circuits

2014 ◽  
Vol 13 (02) ◽  
pp. 1450012 ◽  
Author(s):  
Manorama Chauhan ◽  
Ravindra Singh Kushwah ◽  
Pavan Shrivastava ◽  
Shyam Akashe
Keyword(s):  
Integrated Circuits ◽  
Metal Oxide ◽  
Low Power ◽  
High Performance ◽  
Complementary Metal Oxide Semiconductor ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Short Channel ◽  
State Dependency ◽  
Low Leakage

In the world of Integrated Circuits, complementary metal–oxide–semiconductor (CMOS) has lost its ability during scaling beyond 50 nm. Scaling causes severe short channel effects (SCEs) which are difficult to suppress. FinFET devices undertake to replace usual Metal Oxide Semiconductor Field Effect Transistor (MOSFETs) because of their better ability in controlling leakage and diminishing SCEs while delivering a strong drive current. In this paper, we present a relative examination of FinFET with the double gate MOSFET (DGMOSFET) and conventional bulk Si single gate MOSFET (SGMOSFET) by using Cadence Virtuoso simulation tool. Physics-based numerical two-dimensional simulation results for FinFET device, circuit power is presented, and classifying that FinFET technology is an ideal applicant for low power applications. Exclusive FinFET device features resulting from gate–gate coupling are conversed and efficiently exploited for optimal low leakage device design. Design trade-off for FinFET power and performance are suggested for low power and high performance applications. Whole power consumptions of static and dynamic circuits and latches for FinFET device, believing state dependency, show that leakage currents for FinFET circuits are reduced by a factor of over ~ 10X, compared to DGMOSFET and ~ 20X compared with SGMOSFET.

Simulations and Modeling of TFET for Low Power Design

2016 ◽  
pp. 640-667 ◽  
Author(s):  
Sunil Kumar ◽  
Balwinder Raj
Keyword(s):  
Low Power ◽  
Semiconductor Industry ◽  
Complementary Metal Oxide Semiconductor ◽  
Low Power Design ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Manufacturing Cost ◽  
Technology Advancement ◽  
Channel Effects ◽  
Tunnel Fets

In Complementary Metal-Oxide-Semiconductor (CMOS) technology, scaling has been a main key for continuous progress in silicon-based semiconductor industry over the past four decades. However, as the technology advancement on nanometer scale regime for the purpose of building ultra-high density integrated electronic computers and extending performance, CMOS devices are facing fundamental problems such as increased leakage currents, large process parameter variations, short channel effects, increase in manufacturing cost, etc. The new technology must be energy efficient, dense, and enable more device function per unit area and time. There are many novel nanoscale semiconductor devices, this book chapter introduces and summarizes progress in the development of the Tunnel Field-Effect Transistors (TFETs) for low power design. Tunnel FETs are interesting devices for ultra-low power applications due to their steep sub-threshold swing (SS) and very low OFF-current. Tunnel FETs avoid the limit 60mv/decade by using quantum-mechanical Band-to-Band Tunneling (BTBT).

Sign in / Sign up

Export Citation Format

Share Document