scholarly journals Excel Methods to Design and Validate in Microelectronics (Complementary Metal–Oxide–Semiconductor, CMOS) for Biomedical Instrumentation Application

Sensors ◽  
2021 ◽  
Vol 21 (22) ◽  
pp. 7486
Author(s):  
Graciano Dieck-Assad ◽  
José Manuel Rodríguez-Delgado ◽  
Omar Israel González Peña
Keyword(s):  
Integrated Circuits ◽  
Degrees Of Freedom ◽  
Low Voltage ◽  
Complementary Metal Oxide Semiconductor ◽  
Open Science ◽  
Oxide Semiconductor ◽  
Instrumentation Amplifier ◽  
Short Channel ◽  
Transconductance Amplifier ◽  
Cmos Mems

CMOS microelectronics design has evolved tremendously during the last two decades. The evolution of CMOS devices to short channel designs where the feature size is below 1000 nm brings a great deal of uncertainty in the way the microelectronics design cycle is completed. After the conceptual idea, developing a thinking model to understand the operation of the device requires a good “ballpark” evaluation of transistor sizes, decision making, and assumptions to fulfill the specifications. This design process has iterations to meet specifications that exceed in number of the available degrees of freedom to maneuver the design. Once the thinking model is developed, the simulation validation follows to test if the design has a good possibility of delivering a successful prototype. If the simulation provides a good match between specifications and results, then the layout is developed. This paper shows a useful open science strategy, using the Excel software, to develop CMOS microelectronics hand calculations to verify a design, before performing the computer simulation and layout of CMOS analog integrated circuits. The full methodology is described to develop designs of passive components, as well as CMOS amplifiers. The methods are used in teaching CMOS microelectronics to students of electronic engineering with industrial partner participation. This paper describes an exhaustive example of a low-voltage operational transconductance amplifier (OTA) design which is used to design an instrumentation amplifier. Finally, a test is performed using this instrumentation amplifier to implement a front-end signal conditioning device for CMOS-MEMS biomedical applications.

Analysis and Simulation of a Low-Leakage Analog Single Gate and FinFET Circuits

2014 ◽  
Vol 13 (02) ◽  
pp. 1450012 ◽  
Author(s):  
Manorama Chauhan ◽  
Ravindra Singh Kushwah ◽  
Pavan Shrivastava ◽  
Shyam Akashe
Keyword(s):  
Integrated Circuits ◽  
Metal Oxide ◽  
Low Power ◽  
High Performance ◽  
Complementary Metal Oxide Semiconductor ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Short Channel ◽  
State Dependency ◽  
Low Leakage

In the world of Integrated Circuits, complementary metal–oxide–semiconductor (CMOS) has lost its ability during scaling beyond 50 nm. Scaling causes severe short channel effects (SCEs) which are difficult to suppress. FinFET devices undertake to replace usual Metal Oxide Semiconductor Field Effect Transistor (MOSFETs) because of their better ability in controlling leakage and diminishing SCEs while delivering a strong drive current. In this paper, we present a relative examination of FinFET with the double gate MOSFET (DGMOSFET) and conventional bulk Si single gate MOSFET (SGMOSFET) by using Cadence Virtuoso simulation tool. Physics-based numerical two-dimensional simulation results for FinFET device, circuit power is presented, and classifying that FinFET technology is an ideal applicant for low power applications. Exclusive FinFET device features resulting from gate–gate coupling are conversed and efficiently exploited for optimal low leakage device design. Design trade-off for FinFET power and performance are suggested for low power and high performance applications. Whole power consumptions of static and dynamic circuits and latches for FinFET device, believing state dependency, show that leakage currents for FinFET circuits are reduced by a factor of over ~ 10X, compared to DGMOSFET and ~ 20X compared with SGMOSFET.

Realization of Fractional-Order Double-Scroll Chaotic System Using Operational Transconductance Amplifier (OTA)

2017 ◽  
Vol 27 (01) ◽  
pp. 1850006 ◽  
Author(s):  
Mohammad Rafiq Dar ◽  
Nasir Ali Kant ◽  
Farooq Ahmad Khanday
Keyword(s):  
Fractional Order ◽  
Chaotic System ◽  
Low Voltage ◽  
Complementary Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Operational Transconductance Amplifiers ◽  
System A ◽  
Transconductance Amplifier ◽  
Theoretical Predictions

Realization of fractional-order double-scroll chaotic system using Operational Transconductance Amplifiers (OTAs) as active elements are presented in this paper. The fractional-order double-scroll chaotic system has been studied before as well using passive RC-ladder and tree-based structures but in this paper the requisite fractional-order integration has been accomplished through an integer-order multiple-feedback topology. As compared to double or multiple scroll chaotic systems existing in the open literature, the proposed realization offers the advantages of (a) low-voltage implementation, (b) integrablity as the design is resistor- and inductor-less and only grounded components have been employed in the design, and, (c) electronic tunability of the fractional order, time-constants and gain factors. In order to demonstrate the usefulness of the chaotic system, a simple secure message communication system has been designed and verified for its operation. The theoretical predictions of the proposed implementations have been verified by using 0.35[Formula: see text][Formula: see text]m complementary metal oxide semiconductor (CMOS) process file provided by Austrian Micro System (AMS).

scholarly journals Optimal design of CMOS current mode instrumentation amplifier using bio-inspired method for biomedical applications

2022 ◽  
Vol 25 (1) ◽  
pp. 120
Author(s):  
Issa Sabiri ◽  
Hamid Bouyghf ◽  
Abdelhadi Raihani ◽  
Brahim Ouacha
Keyword(s):  
Integrated Circuits ◽  
Biomedical Applications ◽  
Complementary Metal Oxide Semiconductor ◽  
Current Mode ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Design System ◽  
Instrumentation Amplifier ◽  
Large Bandwidth ◽  
Bee Colony

Analog integrated circuits for biomedical applications require good performance. This paper presents an instrumentation amplifier (IA) design based on three complementary metal oxide semiconductor (CMOS) conveyors with an active resistor. This circuit offers the possibility to control the gain by voltage and current. We have designed the IA to minimize the parasitic resistance (Rx) with large bandwidth and high common mode rejection ratio (CMRR) using the artificial bee colony algorithm (ABC). The topology is simulated using 0.35µm CMOS technology parameters. The optimization problem is represented by an objective function that will be implemented using MATLAB script. The results were approved by the simulation using the advanced design system (ADS) tool. The simulation results were compared to the characteristics of some other instrumentation amplifiers exsisting in the literature. The circuit has a higher CMRR than other topologies.

scholarly journals New Radiation-Hardened Design of a CMOS Instrumentation Amplifier and its Tolerant Characteristic Analysis

Electronics ◽  
2020 ◽  
Vol 9 (3) ◽  
pp. 388 ◽  
Author(s):  
Minwoong Lee ◽  
Seongik Cho ◽  
Namho Lee ◽  
Jongyeol Kim
Keyword(s):  
Integrated Circuits ◽  
Nuclear Power ◽  
Power Plants ◽  
Complementary Metal Oxide Semiconductor ◽  
Low Power Design ◽  
Oxide Semiconductor ◽  
Instrumentation Amplifier ◽  
Negative Effects ◽  
Characteristic Analysis ◽  
Radiation Hardened

A radiation-hardened instrumentation amplifier (IA) that allows precise measurement in radiation environments, including nuclear power plants, space environments, and radiation therapy rooms, was designed and manufactured, and its characteristics were verified. Most electronic systems are currently designed using silicon-based complementary metal-oxide semiconductor (CMOS) integrated circuits (ICs) to achieve a highly integrated low-power design. However, fixed charges induced in silicon by ionization radiation cause various negative effects, resulting in, for example, the generation of leakage current in circuits, performance degradation, and malfunction. Given that such problems in radiation environments may directly lead to a loss of life or environmental contamination, it is critical to implement radiation-hardened CMOS IC technology. In this study, an IA used to amplify fine signals of the sensors was designed and fabricated in the 0.18 μm CMOS bulk process. The IA contained sub-circuits that ensured the stable voltage supply needed to implement system-on-chip (SoC) solutions. It was also equipped with special radiation-hardening technology by applying an I-gate n-MOSFET that blocks the radiation-induced leakage currents. Its ICs were verified to provide the intended performance following a total cumulative dose of up to 25 kGy(Si), ensuring its safety in radiation environments.

scholarly journals Investigation of PVT-Aware STT-MRAM Sensing Circuits for Low-VDD Scenario

Micromachines ◽  
2021 ◽  
Vol 12 (5) ◽  
pp. 551
Author(s):  
Zhongjian Bian ◽  
Xiaofeng Hong ◽  
Yanan Guo ◽  
Lirida Naviner ◽  
Wei Ge ◽  
...  
Keyword(s):  
Nonvolatile Memory ◽  
High Speed ◽  
Low Voltage ◽  
Supply Voltage ◽  
Random Access ◽  
Magnetic Tunnel Junction ◽  
Complementary Metal Oxide Semiconductor ◽  
Current Mode ◽  
Cmos Technology ◽  
Oxide Semiconductor

Spintronic based embedded magnetic random access memory (eMRAM) is becoming a foundry validated solution for the next-generation nonvolatile memory applications. The hybrid complementary metal-oxide-semiconductor (CMOS)/magnetic tunnel junction (MTJ) integration has been selected as a proper candidate for energy harvesting, area-constraint and energy-efficiency Internet of Things (IoT) systems-on-chips. Multi-VDD (low supply voltage) techniques were adopted to minimize energy dissipation in MRAM, at the cost of reduced writing/sensing speed and margin. Meanwhile, yield can be severely affected due to variations in process parameters. In this work, we conduct a thorough analysis of MRAM sensing margin and yield. We propose a current-mode sensing amplifier (CSA) named 1D high-sensing 1D margin, high 1D speed and 1D stability (HMSS-SA) with reconfigured reference path and pre-charge transistor. Process-voltage-temperature (PVT) aware analysis is performed based on an MTJ compact model and an industrial 28 nm CMOS technology, explicitly considering low-voltage (0.7 V), low tunneling magnetoresistance (TMR) (50%) and high temperature (85 °C) scenario as the worst sensing case. A case study takes a brief look at sensing circuits, which is applied to in-memory bit-wise computing. Simulation results indicate that the proposed high-sensing margin, high speed and stability sensing-sensing amplifier (HMSS-SA) achieves remarkable performance up to 2.5 GHz sensing frequency. At 0.65 V supply voltage, it can achieve 1 GHz operation frequency with only 0.3% failure rate.

scholarly journals Extremely high-gain source-gated transistors

2019 ◽  
Vol 116 (11) ◽  
pp. 4843-4848 ◽  
Author(s):  
Jiawei Zhang ◽  
Joshua Wilson ◽  
Gregory Auton ◽  
Yiming Wang ◽  
Mingsheng Xu ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Indium Tin Oxide ◽  
High Performance ◽  
Critical Factor ◽  
High Gain ◽  
Oxide Semiconductor ◽  
Design Rule ◽  
Short Channel ◽  
Channel Effects ◽  
Channel Lengths

Despite being a fundamental electronic component for over 70 years, it is still possible to develop different transistor designs, including the addition of a diode-like Schottky source electrode to thin-film transistors. The discovery of a dependence of the source barrier height on the semiconductor thickness and derivation of an analytical theory allow us to propose a design rule to achieve extremely high voltage gain, one of the most important figures of merit for a transistor. Using an oxide semiconductor, an intrinsic gain of 29,000 was obtained, which is orders of magnitude higher than a conventional Si transistor. These same devices demonstrate almost total immunity to negative bias illumination temperature stress, the foremost bottleneck to using oxide semiconductors in major applications, such as display drivers. Furthermore, devices fabricated with channel lengths down to 360 nm display no obvious short-channel effects, another critical factor for high-density integrated circuits and display applications. Finally, although the channel material of conventional transistors must be a semiconductor, by demonstrating a high-performance transistor with a semimetal-like indium tin oxide channel, the range and versatility of materials have been significantly broadened.

scholarly journals Portable Real-Time Detection of Pb(II) Using a CMOS MEMS-Based Nanomechanical Sensing Array Modified with PEDOT:PSS

Nanomaterials ◽  
2020 ◽  
Vol 10 (12) ◽  
pp. 2454
Author(s):  
Yi-Kuang Yen ◽  
Chao-Yu Lai
Keyword(s):  
Limit Of Detection ◽  
Quality Measurement ◽  
Complementary Metal Oxide Semiconductor ◽  
Cost Effective ◽  
Sample Volume ◽  
Small Sample ◽  
Oxide Semiconductor ◽  
Resistance Change ◽  
Site Water ◽  
Cmos Mems

Detecting the concentration of Pb2+ ions is important for monitoring the quality of water due to it can become a health threat as being in certain level. In this study, we report a nanomechanical Pb2+ sensor by employing the complementary metal-oxide-semiconductor microelectromechanical system (CMOS MEMS)-based piezoresistive microcantilevers coated with PEDOT:PSS sensing layers. Upon reaction with Pb2+, the PEDOT:PSS layer was oxidized which induced the surface stress change resulted in a subsequent bending of the microcantilever with the signal response of relative resistance change. This sensing platform has the advantages of being mass-produced, miniaturized, and portable. The sensor exhibited its sensitivity to Pb2+ concentrations in a linear range of 0.01–1000 ppm, and the limit of detection was 5 ppb. Moreover, the sensor showed the specificity to Pb2+, required a small sample volume and was easy to operate. Therefore, the proposed analytical method described here may be a sensitive, cost-effective and portable sensing tool for on-site water quality measurement and pollution detection.

scholarly journals Low-Cost 2D Index and Straightness Measurement System Based on a CMOS Image Sensor

Sensors ◽  
2019 ◽  
Vol 19 (24) ◽  
pp. 5461 ◽  
Author(s):  
Alain Küng ◽  
Benjamin A. Bircher ◽  
Felix Meli
Keyword(s):  
Measurement System ◽  
Degrees Of Freedom ◽  
Low Cost ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Image Sensor ◽  
Image Sensor ◽  
Oxide Semiconductor ◽  
Measurement Systems ◽  
Starting Point ◽  
Sensor Properties

Accurate traceable measurement systems often use laser interferometers for position measurements in one or more dimensions. Since interferometers provide only incremental information, they are often combined with index sensors to provide a stable reference starting point. Straightness measurements are important for machine axis correction and for systems having several degrees of freedom. In this paper, we investigate the accuracy of an optical two-dimensional (2D) index sensor, which can also be used in a straightness measurement system, based on a fiber-coupled, collimated laser beam pointing onto an image sensor. Additionally, the sensor can directly determine a 2D position over a range of a few millimeters. The device is based on a simple and low-cost complementary metal–oxide–semiconductor (CMOS) image sensor chip and provides sub-micrometer accuracy. The system is an interesting alternative to standard techniques and can even be implemented on machines for real-time corrections. This paper presents the developed sensor properties for various applications and introduces a novel error separation method for straightness measurements.

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