High-Mobility SiC MOSFETs Using a Thin-SiO2/Al2O3 Gate Stack

2018 ◽  
Vol 924 ◽  
pp. 494-497 ◽  
Author(s):  
Jesus Urresti ◽  
Faiz Arith ◽  
Konstantin Vassilevski ◽  
Amit Kumar Tiwari ◽  
Sarah Olsen ◽  
...  
Keyword(s):  
High Temperature ◽  
Low Temperature ◽  
High Mobility ◽  
Gate Oxide ◽  
Interface Traps ◽  
Gate Stack ◽  
Mos Capacitors ◽  
Channel Mobility

We report the development of a low-temperature (600 °C) gate oxidation approach to minimize the density of interface traps (DIT) at the SiC/SiO2interface, ultimately leading to a significantly higher channel mobility in SiC MOSFETs of 81 cm2·V-1·s-1, >11x higher than devices fabricated alongside but with a conventional 1150 °C gate oxide. We further report on the comparison made between the DITand channel mobilities of MOS capacitors and n-MOSFETs fabricated using the low-and high-temperature gate oxidation.

Gamma Irradiation Effects on 4H-SiC MOS Capacitors and MOSFETs

2006 ◽  
Vol 527-529 ◽  
pp. 1063-1066 ◽  
Author(s):  
Ayayi Claude Ahyi ◽  
S.R. Wang ◽  
John R. Williams
Keyword(s):  
Field Effect ◽  
Gamma Dose ◽  
Interface Traps ◽  
Valence Band Edge ◽  
Field Effect Mobility ◽  
Irradiation Effects ◽  
Mos Capacitors ◽  
Channel Mobility ◽  
Radiation Induced ◽  
Radiation Tolerant

The effects of gamma radiation on field effect mobility and threshold voltage have been studied for lateral n-channel 4H-SiC MOSFETs passivated with nitric oxide. MOS capacitors (n and p) and n-channel lateral MOSFETs were irradiated unbiased (floating contacts) for a total gamma dose of 6.8Mrad (Si). The MOS capacitors were used to study the radiation-induced interface traps and fixed oxide charge that affect the performance of the MOSFETs. Radiationinduced interface traps were observed near the SiC valence band edge and just above mid-gap, and field effect channel mobility was reduced by 18-20% following irradiation. Even so, 4HMOSFETs appear to be more radiation tolerant than Si devices.

Compatibility of POCl3 Gate Process with the Fabrication of Vertical 4H-SiC MOSFETs

2020 ◽  
Vol 1004 ◽  
pp. 565-570
Author(s):  
Tomokatsu Watanabe ◽  
Munetaka Noguchi ◽  
Shingo Tomohisa ◽  
Naruhisa Miura
Keyword(s):  
Thermal Treatment ◽  
Low Temperature ◽  
Negative Charge ◽  
Charge Trapping ◽  
Gate Oxide ◽  
Device Fabrication ◽  
Post Processing ◽  
Production Lines ◽  
Channel Mobility ◽  
Device Operation

We used the POCl3 gate technique for the fabrication of 4H-SiC vertical MOSFETs, and examined its effect on the VTH-RON tradeoff and the compatibility with device fabrication. The gate oxide film was formed by thermal dry O2 oxidation followed by POCl3 or NO annealing. The POCl3 process reduced RON by about 30% compared with the NO process for the ones having VTH of 1.1 V, being attributed to the channel mobility enhancement. Moreover, the improvement was more effective for higher VTH designs. The conventional thermal treatment after the gate process considerably spoiled the channel mobility improvement brought by the POCl3 annealing and strengthened negative charge trapping in the gate oxide. The presumed extra-formed defects also affected the EOX dependence of tBD on the TDDB tests, being expected to shorten the gate oxide lifetime under practical device operation stress. Successful insertion of the POCl3 process into production lines depends upon careful low-temperature post processing.

Electron Scattering in Buried InGaAs MOSFET Channel with HfO2 Gate Oxide

2009 ◽  
Vol 1155 ◽  
Author(s):  
Serge Oktyabrsky ◽  
Padmaja Nagaiah ◽  
Vadim Tokranov ◽  
Sergei Koveshnikov ◽  
Michael Yakimov ◽  
...  
Keyword(s):  
High Mobility ◽  
Gate Oxide ◽  
Cmos Technology ◽  
Interface Layer ◽  
Oxide Interface ◽  
Channel Mobility ◽  
Group Iii ◽  
High K ◽  
Electron Transport Properties ◽  
Group Iii V Semiconductor

AbstractGroup III-V semiconductor materials are being studied as potential replacements for conventional CMOS technology due to their better electron transport properties. However, the excess scattering of carriers in MOSFET channel due to high-k gate oxide interface significantly depreciates the benefits of III-V high-mobility channel materials. We present results on Hall electron mobility of buried QW structures influenced by remote scattering due to InGaAs/HfO2 interface. Mobility in In0.77Ga0.23As QWs degraded from 12000 to 1200 cm2/V-s and the mobility vs. temperature slope changed from T-1.2 to almost T+1.0 in 77-300 K range when the barrier thickness is reduced from 50 to 0 nm. This mobility change is attributed to remote Coulomb scattering due to charges and dipoles at semiconductor/oxide interface. Elimination of the InGaAs/HfO2 interface via introduction of SiOx interface layer formed by oxidation of thin a-Si passivation layer was found to improve the channel mobility. The mobility vs. sheet carrier density shows the maximum close to 2×1012 cm-2.

S-Passivation of the Ge Gate Stack Using (NH4)2S

2012 ◽  
Vol 187 ◽  
pp. 23-26 ◽  
Author(s):  
Sonja Sioncke ◽  
Claudia Fleischmann ◽  
Dennis Lin ◽  
Evi Vrancken ◽  
Matty Caymax ◽  
...  
Keyword(s):  
High Mobility ◽  
Gate Oxide ◽  
Gate Stack ◽  
Process Flow ◽  
Oxide Deposition

The last decennia, a lot of effort has been made to introduce new channel materials in a Si process flow. High mobility materials such as Ge need a good gate stack passivation in order to ensure optimal MOSFET operation. Several routes for passivating the Ge gate stack have been explored in the last years. We present here the S-passivation of the Ge gate stack: (NH4)2S is used to create a S-terminated Ge surface. In this paper the S-treatment is discussed. The S-terminated Ge surface is not chemically passive but can still react with air. After gate oxide deposition, the Ge-S bonds are preserved and an adequate passivation is found for pMOS operation.

The Electrical Phenomena of Non-planar Structure and Devices using Plasma Doping

2005 ◽  
Vol 864 ◽  
Author(s):  
Jong-Heon Yang ◽  
In-Bok Baek ◽  
Kiju Im ◽  
Chang-Geun Ahn ◽  
Sungkweon Baek ◽  
...  
Keyword(s):  
High Temperature ◽  
Low Temperature ◽  
Thermal Annealing ◽  
Gate Oxide ◽  
Subthreshold Slope ◽  
Oxide Interface ◽  
Substrate Heating ◽  
Plasma Doping ◽  
Device Reliability ◽  
Research Show

AbstractWe fabricated narrow fins structures and non-planar MOSFETs like FinFETs and triple-gate MOSFETs using plasma doping with substrate heating under 350··, and measured their I-V characteristics. Fins and MOSFETs using low-temperature doping process show good current drivability and low subthreshold slope. However, without post high-temperature thermal annealing, this process could not avoid generating defects and traps as well as mobile protons on the gate and gate oxide interface and junctions, and therefore degraded device reliability. The results of ultra-small MOSFET research show possibility of new memory devices with these traps and ions in devices.

Electrical Properties of High-K LaLuO3 Gate Oxide for SOI MOSFETs

2011 ◽  
Vol 276 ◽  
pp. 87-93
Author(s):  
Y.Y. Gomeniuk ◽  
Y.V. Gomeniuk ◽  
A. Nazarov ◽  
P.K. Hurley ◽  
Karim Cherkaoui ◽  
...  
Keyword(s):  
Electrical Characterization ◽  
Gate Oxide ◽  
Interface State ◽  
Channel Length ◽  
State Density ◽  
Interface State Density ◽  
Mos Capacitors ◽  
Channel Mobility ◽  
Threshold Voltages

The paper presents the results of electrical characterization of MOS capacitors and SOI MOSFETs with novel high-κ LaLuO3 dielectric as a gate oxide. The energy distribution of interface state density at LaLuO3/Si interface is presented and typical maxima of 1.2×1011 eV–1cm–2 was found at about 0.25 eV from the silicon valence band. The output and transfer characteristics of the n- and p-MOSFET (channel length and width were 1 µm and 50 µm, respectively) are presented. The front channel mobility appeared to be 126 cm2V–1s–1 and 70 cm2V–1s–1 for n- and p-MOSFET, respectively. The front channel threshold voltages as well as the density of states at the back interface are presented.

Fabrication of 4H-SiC p-Channel MOSFET with High Channel Mobility

2006 ◽  
Vol 527-529 ◽  
pp. 1301-1304
Author(s):  
Mitsuo Okamoto ◽  
Mieko Tanaka ◽  
Tsutomu Yatsuo ◽  
Kenji Fukuda
Keyword(s):  
Valence Band ◽  
Oxidation Process ◽  
Gate Oxide ◽  
Interface States ◽  
Wet Oxidation ◽  
Mos Capacitors ◽  
Channel Mobility ◽  
Dry Oxidation ◽  
Low Threshold ◽  
P Type

We have fabricated inversion-type p-channel MOSFETs on 4H-SiC substrates. In this paper, influences of gate oxidation process on the properties of p-channel MOSFETs were investigated. The gate oxide was formed under these three conditions: (i) dry oxidation, (ii) dry oxidation following wet re-oxidation, and (iii) wet oxidation. The C-V measurements of p-type 4H-SiC MOS capacitors revealed that wet oxidation process reduced the interface states near the valence band. The p-channel MOSFET with low interface states near the valence band indicated low threshold voltage (Vth), high field effect channel mobility (μFE) and low subthreshold swing (S). We obtained 4H-SiC p-channel MOSFET with high μFE of 15.6cm2/Vs by using wet oxidation as gate oxidation process.

Influence of Annealing, Oxidation and Doping on Conduction-Band near Interface Traps in 4H-SiC Characterized by Low Temperature Conductance Measurements

2015 ◽  
Vol 821-823 ◽  
pp. 476-479
Author(s):  
Stefan Noll ◽  
Martin Rambach ◽  
Michael Grieb ◽  
Dick Scholten ◽  
Anton J. Bauer ◽  
...  
Keyword(s):  
Low Temperature ◽  
Conduction Band ◽  
Nitrogen Doping ◽  
Interface Traps ◽  
Channel Mobility ◽  
High Frequencies ◽  
Inversion Channel ◽  
Very High Frequencies ◽  
Post Implantation ◽  
Very High

Current power MOSFET devices on Silicon Carbide show a limited inversion channel mobility, which can be a result of the expected very high density of interface states near the conduction band . In the current work, the effect of the post implantation annealing temperature, the thermal oxidation and the nitrogen doping of the n-epi layer on the density of these interface traps is investigated using capacity-conductance measurements. Instead of the usage of very high frequencies as used in , in this investigation the measurements were performed in liquid nitrogen to decrease the recharging times of the interface traps.Due to the different processing the samples showed a wide spreading of the inversion channel mobility. The conductance measurements show a characteristic peak caused by the conduction band near interface traps especially for the low temperature measurements. But these traps could not be correlated to the mobility. Instead, a correlation to the nitrogen doping of the epi layer could be observed.

A Comparison of Active Near-Interface Traps in Nitrided and As-Grown Gate Oxides by the Direct Measurement Technique

2020 ◽  
Vol 1004 ◽  
pp. 635-641
Author(s):  
Peyush Pande ◽  
Sima Dimitrijev ◽  
Daniel Haasmann ◽  
Hamid Amini Moghadam ◽  
Philip Tanner ◽  
...  
Keyword(s):  
Nitric Oxide ◽  
Comparative Analysis ◽  
Direct Measurement ◽  
Measurement Technique ◽  
Measurement Method ◽  
Gate Oxide ◽  
Interface Traps ◽  
Gate Oxides ◽  
Mos Capacitors ◽  
Direct Measurement Method

This paper presents a comparative analysis of the electrically active near-interface traps, energetically located above the bottom of conduction band. Two different samples of N-type SiC MOS capacitors were fabricated with gate oxides grown in (1) dry O2 (as-grown) and (2) dry O2 annealed in nitric oxide (nitride). Measurements performed by the direct measurement method revealed that the traps located further away from the SiO2/SiC interface are removed by nitridation. A spatially localized behaviour of NITs is observed only in the nitrided gate oxide but not in the as-grown gate oxide.

High Temperature Rapid Thermal Oxidation and Nitridation of 4H-SiC in Diluted N2O and NO Ambient

2005 ◽  
Vol 483-485 ◽  
pp. 669-672 ◽  
Author(s):  
Ryouji Kosugi ◽  
Kenji Fukuda ◽  
Kazuo Arai
Keyword(s):  
High Temperature ◽  
Gate Oxide ◽  
Process Time ◽  
Oxide Formation ◽  
Mos Capacitor ◽  
Channel Mobility ◽  
Oxidation Rates ◽  
Capacitance Voltage ◽  
Total Process ◽  
Ambient Gases

A high temperature rapid thermal processing (HT-RTP) above 1400oC was investigated for use in the gate oxide formation of 4H-SiC by a cold-wall oxidation furnace. The gate oxide film of ~50nm can be formed for several minutes in the oxidizing atmospheres such as N2O and O2, where the oxidation rates were 8-10nm/min. After the initial oxide formation, the HT-RTPs in various ambient gases were conducted, and the dependences of their MOS interface properties on the gases were evaluated by a capacitance-voltage (CV) measurement. Based on the results, the process sequence of gate oxidation was determined as follows; the initial oxide was formed by the HT-RTO (oxidation) in N2O or in O2 with subsequent post annealing in Ar ambient, and then the HT-RTN (nitridation) in NO was conducted. The total process time becomes 20-50min. The interface trap density (Dit) of fabricated MOS capacitor shows 3-5x1011cm-2eV-1 at Ec-E~0.2eV. The field-effect channel mobility of fabricated 4H-SiC lateral MOSFETs was ~30cm2/Vs.

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