Structural and Electrical Characterization of Hydrophobic Direct-Bonded Silicon Interfaces

1993 ◽  
Vol 318 ◽  
Author(s):  
Gordon Tam ◽  
F. Secco d'Aragona ◽  
N. David Theodore
Keyword(s):  
Wafer Bonding ◽  
Electrical Characterization ◽  
Device Fabrication ◽  
High Resistivity ◽  
Electrical Behavior ◽  
Cross Sectional ◽  
Spreading Resistance ◽  
Bonded Interface ◽  
Transmission Electron ◽  
Direct Wafer Bonding

ABSTRACTDirect wafer bonding is a viable technique for fabricating high-voltage devices. An understanding of the microstructure and electrical behavior of the bonded interface is critical for device fabrication. In this paper, we investigated the microstructure of the silicon-to-silicon bonded interface using cross-sectional transmission electron microscopy and the corresponding electrical behavior using spreading resistance probing. Results indicate that oxide precipitates were present at the bonded interface when Czochralski silicon wafer were used in the process. Oxide precipitates were noticeably absent from the bonded interface when float zone wafers were bonded to each other. We find that oxide precipitates at the interface arise not due to the residual oxide at the surface prior to wafer bonding but due to gettering of oxygen from the Czochralski wafer. Spreading resistance measurements show occurrence of a high resistivity region at the bonding interface whether or not oxide precipitates are present.

Observation of the Wurtzite Phase in OMVPE Grown ZnSe/GaAs: Effect on Implantation and Rapid Thermal Annealing

1989 ◽  
Vol 147 ◽  
Author(s):  
K. S. Jones ◽  
J. Yu ◽  
P. D. Lowen ◽  
D. Kisker
Keyword(s):  
Thermal Annealing ◽  
Rapid Thermal Annealing ◽  
Electrical Transport ◽  
High Resistivity ◽  
Ion Milling ◽  
Electrical Transport Properties ◽  
Wurtzite Phase ◽  
Cross Sectional ◽  
Transmission Electron ◽  
Diffraction Patterns

AbstractTransmission electron diffraction patterns of cross-sectional TEM samples of OMVPE ZnSe on GaAs indicate the existence of the hexagonal wurtzite phase in the epitaxial layers. The orientation relationship is (0002)//(111); (1120)//(220). Etching studies indicate the phase is internal not ion milling induced. The average wurtzite particle size is 80Å-120Å. Because of interplanar spacing matches it is easily overlooked. Electrical property measurements show a high resistivity (1010ω/square) which drops by four orders of magnitude upon rapid thermal annealing between 700°C and 900 °C for 3 sec. Implantation of Li and N have little effect on the electrical transport properties. The Li is shown to have a high diffusivity, a solid solubility of ≈1016/cm3 at 800°C and getters to the ZnSeA/aAs interface.

Reconstruction of a High Angle Tilt (110)/(001) Boundary in Si Using O-lattice Theory

2011 ◽  
Vol 178-179 ◽  
pp. 489-494
Author(s):  
Nikolay Cherkashin ◽  
Oleg Kononchuk ◽  
Martin Hÿtch
Keyword(s):  
Wafer Bonding ◽  
Geometric Phase ◽  
Lattice Theory ◽  
Covalent Bonding ◽  
High Angle ◽  
Experimental Identification ◽  
Transmission Electron ◽  
Direct Wafer Bonding ◽  
Geometric Phase Analysis ◽  
High Resolution Tem

High angle close to 90° tilt Si boundary created by direct wafer bonding (DWB) using SmartCut® technology is studied in this work. Experimental identification of defects and morphologies at the interface is realized using conventional transmission electron microscopy (TEM) and geometric phase analysis (GPA) of high-resolution TEM images. Atom reconstruction of the interface along the direction is carried out within the frame of the O-lattice theory. We demonstrate that to preserve covalent bonding across the interface it should consist of facets intersected by a maximum of six planes with three 90° Shockley dislocations per facet. For a long enough interface the formation of Frank dislocations is predicted with a period equal 6 times that of Shockley dislocations. Long range undulations of the interface are shown to be related directly to a deviation from exact 90° tilt of the layer with respect to the substrate.

Structural and electrical characterization of carbon nanotube interconnects by combined transmission electron microscopy and scanning spreading resistance microscopy

2011 ◽  
Vol 1349 ◽  
Author(s):  
Thomas Hantschel ◽  
Xiaoxing Ke ◽  
Nicolo’ Chiodarelli ◽  
Andreas Schulze ◽  
Hugo Bender ◽  
...  
Keyword(s):  
Electron Microscopy ◽  
Transmission Electron Microscopy ◽  
Integrated Circuits ◽  
Quantitative Measurement ◽  
Electrical Characterization ◽  
Research Needs ◽  
Spreading Resistance ◽  
Transmission Electron ◽  
Plane View

ABSTRACTThe use of carbon nanotubes (CNT) as interconnects in future integrated circuits (IC) is being considered as a replacement for copper. As this research needs also innovative metrology solutions, we have developed a combined approach for the plane-view analysis of CNT integrated in contact holes where transmission electron microscopy (TEM) enables the quantitative measurement of density and structure of the CNT and where scanning spreading resistance microscopy (SSRM) is used to electrically map the distribution of the CNT. This paper explains the used methodologies in detail and presents results from 300 nm diameter contact holes filled with CNT of 8-12 nm in diameter and a density of about 2 x 1011 cm-2.

Polysilicon nanogap structure development using size expansion technique

2011 ◽  
Vol 28 (3) ◽  
pp. 24-30 ◽  
Author(s):  
Uda Hashim ◽  
Nazwa Taib ◽  
Thikra S. Dhahi ◽  
Azizullah Saifullah
Keyword(s):  
Design Methodology ◽  
Electrical Characterization ◽  
Active Surface ◽  
Device Fabrication ◽  
Electrical Behavior ◽  
Structure Development ◽  
Content Type ◽  
Expansion Technique ◽  
Fabrication And Characterization ◽  
Scanning Electron

PurposeNanobiosensors based on nanogap capacitor are widely used for measuring dielectric properties of DNA, protein and biomolecule. The purpose of this paper is to report on the fabrication and characterization polysilicon nanogap patterning using novelties technique.Design/methodology/approachOverall, the polysilicon nanogap pattern was fabricated based on conventional lithographic techniques. For size expansion technique, by employing simple dry thermal oxidation, the couple of nanogap pattern has been expanded to lowest nanogap value. The progress of nanogap pattern expansion was verified by using scanning electron microscopy (SEM). Conductivity, resistivity, and capacitance test were performed to characterize and to measure electrical behavior of full device fabrication.FindingsSEM characterization emphasis on the expansion of polysilicon nanogap pattern increasing with respect to oxidation time. Electrical characterization shows that nanogap enhanced the sensitivity of the device at the value of nano ampere of current.Originality/valueThese simple least‐cost method does not require complicated nanolithography method of fabrication but still possible to serve as biomolecular junction. This approach can be applied extensively to different design of nanogap structure down to several nanometer levels of dimensions. A method of preparing a nanogap electrode according to the present innovation has an advantage of providing active surface that can be easily modified for immobilizations of biomolecules.

Wafer Bonding of Diamond Films to Silicon for Silicon-on-Insulator Technology

2001 ◽  
Vol 686 ◽  
Author(s):  
Gleb N. Yushin ◽  
Scott D. Wolter ◽  
Alexander V. Kvit ◽  
Ramon Collazo ◽  
John T. Prater ◽  
...  
Keyword(s):  
Wafer Bonding ◽  
Diamond Films ◽  
Polycrystalline Diamond ◽  
Amorphous Layer ◽  
Silicon On Insulator ◽  
Acoustic Microscopy ◽  
Cross Sectional ◽  
Silicon Carbon ◽  
Transmission Electron ◽  
Silicon On Insulator Technology

AbstractPolycrystalline diamond films previously grown on silicon were polished to an RMS roughness of 15 nm and bonded to the silicon in a dedicated ultrahigh vacuum bonding chamber. Successful bonding under a uniaxial mechanical stress of 32 MPa was observed at temperatures as low as 950°C. Scanning acoustic microscopy indicated complete bonding at fusion temperatures above 1150°C. Cross-sectional transmission electron microscopy later revealed a 30 nm thick intermediate amorphous layer consisting of silicon, carbon and oxygen.

SPFM Pre-Cleaning for formation of Silicon Interfaces by Wafer Bonding

1997 ◽  
Vol 477 ◽  
Author(s):  
Stefan Bengtsson ◽  
Karin Ljungberg
Keyword(s):  
Electrical Properties ◽  
Wafer Bonding ◽  
Silicon Surface ◽  
Room Temperature ◽  
Electrical Characterization ◽  
Preparation Procedure ◽  
Cleaning Process ◽  
Spreading Resistance ◽  
Cleaning Procedure

ABSTRACTThe use of H2SO4:H2O2:HF (SPFM) at low HF concentrations (10 to 1000 ppm) has been investigated as the preparation procedure prior to formation of Si/Si interfaces by wafer bonding. The SPFM cleaning process makes it possible to form a hydrophilic (OH terminated) silicon surface, thereby achieving a spontaneous and strong room temperature bond. Electrical characterization using current vs voltage and spreading resistance measurements shows that this cleaning procedure can be used to form Si/Si junctions with excellent electrical properties. Some of the problems related to hydrophobic wafer bonding can thus be circumvented by the proposed technique.

Si Wafer Bonding: Structural Features of the Interface

2009 ◽  
Vol 156-158 ◽  
pp. 85-90 ◽  
Author(s):  
V.I. Vdovin ◽  
N.D. Zakharov ◽  
Eckhard Pippel ◽  
P. Werner ◽  
M.G. Milvidskii ◽  
...  
Keyword(s):  
Oxide Layer ◽  
Wafer Bonding ◽  
Lattice Mismatch ◽  
Twist Angle ◽  
Structural Features ◽  
High Temperature Annealing ◽  
Bonded Interface ◽  
Transmission Electron ◽  
Kinetics Of ◽  
Si Wafer

Kinetics of oxide layer dissolution and atomic structure of Si-Si interface in Si wafer bonded structures have been investigated by transmission electron microscopy. Samples of Si(001)/SiO2/Si(001) and Si(110)/SiO2/Si(001) structures were fabricated by direct hydrophilic wafer bonding of 200 mm wafers followed by high temperature annealing. It is found that the decomposition rate of oxide layer and formation of Si-Si bonded interface depends very much on lattice mismatch and twist angle.

Growth of Device-Quality Homoepitaxial Diamond Thin Films

1989 ◽  
Vol 162 ◽  
Author(s):  
M. W. Geis
Keyword(s):  
Activation Energy ◽  
Growth Conditions ◽  
Device Fabrication ◽  
Diamond Growth ◽  
High Resistivity ◽  
Boron Doped Diamond ◽  
Boron Doped ◽  
Transmission Electron ◽  
Heavily Doped ◽  
P Type

ABSTRACTDiamond has an electric-field breakdown 20 times that of Si and GaAs, and a saturated velocity twice that of Si. This results in a predicted cut off frequency for high-power diamond transistors 40 times that of similar devices made of Si or GaAs. Boron is the only known impurity that can be used to lightly dope diamond. This p-type dopant has an activation energy of 0.3 to 0.4 eV, which results in high-resistivity material that is undesirable for devices. However, heavily boron doped diamond has a very small activation energy and a low resistivity and is of device quality. Transistors can be designed that use only undoped and heavily doped diamond. One of the steps in a device fabrication sequence is homoepitaxial diamond growth. Lightly and heavily doped homoepitaxial diamond films were characterized by scanning and transmission electron microscopy, x-ray diffraction, measurements of resistivity as a function of temperature, and secondary ion mass spectroscopy. It was found that under appropriate growth conditions these films are of device quality.

Innovative 3C-SiC on SiC via Direct Wafer Bonding

2013 ◽  
Vol 740-742 ◽  
pp. 271-274 ◽  
Author(s):  
Michael R. Jennings ◽  
Amador Pérez-Tomás ◽  
Andrea Severino ◽  
Peter J. Ward ◽  
Arif Bashir ◽  
...  
Keyword(s):  
Wafer Bonding ◽  
Polycrystalline Silicon ◽  
Digital Camera ◽  
Chemical Vapor ◽  
Device Fabrication ◽  
Epitaxial Layers ◽  
Direct Wafer Bonding ◽  
Polycrystalline Silicon Carbide ◽  
Conventional Chemical Vapor Deposition ◽  
Deposition Techniques

In this paper, we report on a novel direct wafer bonding technique; Si (111) wafers to polycrystalline silicon carbide carrier wafers. The purpose of this work is to provide a platform for 3C-SiC epitaxial growth above the wafer bonded Si (111) wafers. We have demonstrated reduced wafer bow, confirmed by optical microscopy together with a digital camera. 3C-SiC epitaxial layers have been grown by conventional chemical vapor deposition techniques above Si/SiC structures. All of these 3C-SiC epitaxial layers are highly crystalline in nature. In the future, the realization of thick, bow-free 3C-SiC layers suitable for power device fabrication is achievable.

Quantitative Studies on the Evolution of the Polysilicon/Silicon Interfacial Oxide Upon Annealing

1990 ◽  
Vol 202 ◽  
Author(s):  
Sergio A. Ajuria ◽  
Rafael Reif
Keyword(s):  
Electron Microscopy ◽  
Transmission Electron Microscopy ◽  
Electrical Characterization ◽  
Cross Sectional ◽  
Cross Bridge ◽  
Quantitative Studies ◽  
Transmission Electron ◽  
Wide Range ◽  
Microscopy Data

ABSTRACTPolysilicon/silicon interfacial oxides are shown by cross-sectional Transmission Electron Microscopy studies to agglomerate upon annealing. In addition to presenting highlights of microscopy results, we report on electrical characterization data obtained from Cross-Bridge Kelvin Resistors. Resistor data not only support a model for agglomeration proven on microscopy data, but also allow for a quantitative macroscopic understanding of the agglomeration of polysilicon/silicon interfacial oxides over a wide range of times and temperatures.

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