Competitive Oxidation During Buried Oxide Formation Using Separation by Plasma Implantation of Oxygen (Spimox)

AbstractWe have recently demonstrated a new implantation technique called SPIMOX (separation by plasma implantation of oxygen) to synthesize silicon-on-insulator structures using plasma immersion ion implantation (PIII) process. the implantation is performed by applying a large negative bias to a Si wafer immersed in an oxygen plasma created by an ECR source. Since the technique has no mass analysis, coexistence of O+ and O2+ ions in oxygen plasma can cause a non-Gaussian profile of the as-implanted oxygen distribution. We observed that during post-implantation annealing, the ripening process of the oxide precipitates depends on depth and concentration of the oxygen peaks. IN addition, implanted oxygen can migrate towards the Si surface during annealing, preventing a continuous buried oxide layer formation. IN this paper, we report our observation on the effect of the implantation profile on the competitions between internal oxidation at different depths and between internal and surface oxidation processes. With an additional He implantation, we demonstrate that the nucleation of oxide precipitation can be enhanced.

Download Full-text

Formation of Silicon on Insulator (Soi) With Separation by Plasma Implantation of Oxygen (Spimox)

MRS Proceedings ◽

10.1557/proc-354-117 ◽

1994 ◽

Vol 354 ◽

Cited By ~ 3

Author(s):

J.B. Liu ◽

S.S.K. Iyer ◽

J. Min ◽

P. Chu ◽

R. Gronsky ◽

...

Keyword(s):

Oxide Layer ◽

Rutherford Backscattering Spectrometry ◽

Silicon On Insulator ◽

Low Oxygen ◽

Double Oxide ◽

Buried Oxide ◽

Transmission Electron ◽

Plasma Immersion Ion Implantation ◽

Post Implantation ◽

Si Wafer

AbstractBuried oxide layers in Si were fabricated using non-mass analyzed plasma immersion ion implantation (PHI). We call this process of making separation by implantation of oxygen (SIMOX) with implantation by PIII as separation by plasma implantation of oxygen (SPIMOX). The implantation was carried out by applying a large negative bias to a Si wafer immersed in an oxygen plasma and a nominal dose of 2 × 1017 cm”2 of oxygen was obtained in less than three minutes. Cross section transmission electron microscopy (XTEM) and Rutherford backscattering spectrometry (RBS) were used to characterize the wafers. Three distinct modes of microstructure development were observed after post implantation annealing. With a low oxygen dose (< 1 × 1017 cm”2 ), isolated silicon dioxide precipitates did not grow large enough to form a continuous oxide layer. With a high oxygen dose ( > 3 × 1017 cm”2 ), however, a single buried oxide layer was observed. By optimizing the concentration ratio of 0+ and 02+ in the plasma and the implant dose, a double oxide layer (Si/oxide/Si/oxide/Si) structure, was produced in a single implantation step.

Download Full-text

The Effects of Annealing Temperature on the Characteristics of Buried Oxide Silicon-On-Insulator

MRS Proceedings ◽

10.1557/proc-53-251 ◽

1985 ◽

Vol 53 ◽

Cited By ~ 1

Author(s):

B.-Y Mao ◽

P.-H. Chang ◽

H.W. Lam ◽

B.W. Shen ◽

J.A. Keenan

Keyword(s):

Annealing Temperature ◽

Silicon Film ◽

Silicon Layer ◽

Silicon On Insulator ◽

Thermal Donor ◽

Buried Oxide ◽

Lower Oxygen ◽

Higher Temperature ◽

Soi Substrates ◽

Post Implantation

ABSTRACTThe effects of post implantation annealing on the properties of buried oxide silicon-on-insulator (SOI) substrates in the temperature range of 1150°C to 1300°C have been studied. Microstructural analyses showed that the crystallinity of the top silicon layer was improved at higher annealing temperature. Lower thermal donor generation at 450°C was observed in SOI annealed at higher temperature. The improvement in microstructure and lower thermal donor generation were correlated to the lower oxygen concentration in the top silicon film.

Download Full-text

Structural changes in silicon-on-insulator material during post-implantation annealing

Proceedings, annual meeting, Electron Microscopy Society of America ◽

10.1017/s0424820100145054 ◽

1986 ◽

Vol 44 ◽

pp. 736-737

Author(s):

C. O. Jung ◽

S. J. Krause ◽

S.R. Wilson

Keyword(s):

Integrated Circuits ◽

Oxide Layer ◽

High Speed ◽

Structural Changes ◽

Device Fabrication ◽

Silicon On Insulator ◽

High Quality ◽

Radiation Hardened ◽

Post Implantation ◽

Very High

Silicon-on-insulator (SOI) structures have excellent potential for future use in radiation hardened and high speed integrated circuits. For device fabrication in SOI material a high quality superficial Si layer above a buried oxide layer is required. Recently, Celler et al. reported that post-implantation annealing of oxygen implanted SOI at very high temperatures would eliminate virtually all defects and precipiates in the superficial Si layer. In this work we are reporting on the effect of three different post implantation annealing cycles on the structure of oxygen implanted SOI samples which were implanted under the same conditions.

Download Full-text

Behavior of contact-silicided TFSOI gate structures

Proceedings, annual meeting, Electron Microscopy Society of America ◽

10.1017/s0424820100172036 ◽

1994 ◽

Vol 52 ◽

pp. 860-861

Author(s):

N. David Theodore ◽

Juergen Foerstner ◽

Peter Fejes

Keyword(s):

Semiconductor Device ◽

Series Resistance ◽

Field Effect Transistors ◽

Silicon Layer ◽

Device Fabrication ◽

Silicon On Insulator ◽

Continuous Layer ◽

Buried Oxide ◽

Device Structures ◽

Thin Silicon

As semiconductor device dimensions shrink and packing-densities rise, issues of parasitic capacitance and circuit speed become increasingly important. The use of thin-film silicon-on-insulator (TFSOI) substrates for device fabrication is being explored in order to increase switching speeds. One version of TFSOI being explored for device fabrication is SIMOX (Silicon-separation by Implanted OXygen).A buried oxide layer is created by highdose oxygen implantation into silicon wafers followed by annealing to cause coalescence of oxide regions into a continuous layer. A thin silicon layer remains above the buried oxide (~220 nm Si after additional thinning). Device structures can now be fabricated upon this thin silicon layer.Current fabrication of metal-oxidesemiconductor field-effect transistors (MOSFETs) requires formation of a polysilicon/oxide gate between source and drain regions. Contact to the source/drain and gate regions is typically made by use of TiSi2 layers followedby Al(Cu) metal lines. TiSi2 has a relatively low contact resistance and reduces the series resistance of both source/drain as well as gate regions

Download Full-text

Simulation Method for Buried Oxide Formation of Separation by Implanted Oxygen Structure during Post-Implantation Thermal Annealing

Japanese Journal of Applied Physics ◽

10.1143/jjap.44.2380 ◽

2005 ◽

Vol 44 (4B) ◽

pp. 2380-2384 ◽

Cited By ~ 3

Author(s):

Motoi Nakao ◽

Koichi Sudoh ◽

Hirofumi Iikawa ◽

Hiroshi Iwasaki ◽

Katsutoshi Izumi

Keyword(s):

Thermal Annealing ◽

Simulation Method ◽

Oxide Formation ◽

Buried Oxide ◽

Post Implantation

Download Full-text

Effects of buried oxide on electrical performance of thin-film silicon-on-insulator metal–oxide–semiconductor field-effect transistor

Journal of Applied Physics ◽

10.1063/1.369763 ◽

1999 ◽

Vol 85 (7) ◽

pp. 3912-3915 ◽

Cited By ~ 7

Author(s):

Jong-Wook Lee ◽

Min-Rok Oh ◽

Yo-Hwan Koh

Keyword(s):

Thin Film ◽

Metal Oxide ◽

Field Effect ◽

Field Effect Transistor ◽

Metal Oxide Semiconductor ◽

Silicon On Insulator ◽

Oxide Semiconductor ◽

Electrical Performance ◽

Buried Oxide ◽

Effect Transistor

Download Full-text

STUDY OF ELECTRICAL CHARACTERISTIC FOR 50NM AND 10NM SOI BODY THICKNESS IN MOSFET DEVICE

Jurnal Teknologi ◽

10.11113/jt.v77.6616 ◽

2015 ◽

Vol 77 (21) ◽

Author(s):

M.N.I.A Aziz ◽

F. Salehuddin ◽

A.S.M. Zain ◽

K.E. Kaharudin

Keyword(s):

Thin Film ◽

Electrical Characteristic ◽

Silicon On Insulator ◽

Electrical Characteristics ◽

Short Channel ◽

Doping Density ◽

Soi Mosfet ◽

Buried Oxide ◽

Soi Technology ◽

Better Than

Silicon-on-insulator (SOI) technology is an effective approach of mitigating the short channel effect (SCE) problems. The SOI is believed to be capable of suppressing the SCE, thereby improving the overall electrical characteristics of MOSFET device. SCE in SOI MOSFET is heavily influenced by thin film thickness, thin-film doping density and buried oxide (BOX) thickness. This paper will analyze the effect of BOX towards SOI MOSFET device. The 50nm and 10nm thickness of buried oxide in SOI MOSFET was developed by using SILVACO TCAD tools, specifically known as Athena and Atlas modules. From the observation, the electrical characteristic of 100nm thickness is slightly better than 50nm and 10nm. It is observed that the value drive current of 10nm and 100nm thickness SOI MOSFET was 6.9% and 11% lower than 50nm respectively, but the overall 50nm is superior. However, the electrical characteristics of 10nm SOI MOSFET are still closer and within the range of ITRS 2013 prediction.

Download Full-text

Effect of Annealing on the Structure of Buried SiO2 Layers Formed By Elevated Temperature High Dose Oxygen Implantation

MRS Proceedings ◽

10.1557/proc-53-257 ◽

1985 ◽

Vol 53 ◽

Cited By ~ 7

Author(s):

S.J. Krause ◽

C.O. Jung ◽

S.R. Wilson ◽

R.P. Lorigan ◽

M.E. Burnham

Keyword(s):

Single Crystal ◽

Oxide Layer ◽

Elevated Temperatures ◽

Superficial Layer ◽

Silicon On Insulator ◽

High Dose ◽

Threading Dislocations ◽

Heater Temperature ◽

Buried Oxide ◽

Structural Differences

ABSTRACTOxygen has been implanted into Si wafers at high doses and elevated temperatures to form a buried SiO2 layer for use in silicon-on-insulator (SOI) structures. Substrate heater temperatures have been varied (300, 400, 450 and 500°C) to determine the effect on the structure of the superficial Si layer through a processing cycle of implantation, annealing, and epitaxial growth. Transmission electron microscopy was used to characterize the structure of the superficial layer. The structure of the samples was examined after implantation, after annealing at 1150°C for 3 hours, and after growth of the epitaxial Si layer. There was a marked effect on the structure of the superficial Si layer due to varying substrate heater temperature during implantation. The single crystal structure of the superficial Si layer was preserved at all implantation temperatures from 300 to 500°C. At the highest heater temperature the superficial Si layer contained larger precipitates and fewer defects than did wafers implanted at lower temperatures. Annealing of the as-implanted wafers significantly reduced structural differences. All wafers had a region of large, amorphous 10 to 50 nm precipitates in the lower two-thirds of the superficial Si layer while in the upper third of the layer there were a few threading dislocations. In wafers implanted at lower temperatures the buried oxide grew at the top surface only. During epitaxial Si growth the buried oxide layer thinned and the precipitate region above and below the oxide layer thickened for all wafers. There were no significant structural differences of the epitaxial Si layer for wafers with different implantation temperatures. The epitaxial layer was high quality single crystal Si and contained a few threading dislocations. Overall, structural differences in the epitaxial Si layer due to differences in implantation temperature were minimal.

Download Full-text