Assessment of Silicon—On—Insulator Technologies for Vlsi

1985 ◽  
Vol 53 ◽  
Author(s):  
B-Y. Tsaur
Keyword(s):  
High Performance ◽  
Cost Effective ◽  
Silicon On Insulator ◽  
Current Status ◽  
High Dose ◽  
Future Prospects ◽  
Device Structures ◽  
Radiation Hardened ◽  
Near Term ◽  
Soi Technology

ABSTRACTA high—performance, cost—effective silicon—on—insulator (SOI) technology would have important near—term applications in radiation—hardened electronics and longer term applications in submicrometer VLSI. The advantages of SOI over bulk Si technology for these applications will be outlined, and CMOS, CJFET, andbipolar device structures being developed for SOI will be discussed. The current status and future prospects of the two most promising SOI technologies —— beam recrystallization and high—dose oxygen implantation —— will be reviewed, with emphasis on such issues critical to commercialization as material quality and manufacturing feasibility.

Recent Progress in SOI Materials and Devices for VLSI Applications

1993 ◽  
Vol 316 ◽  
Author(s):  
H. H. Hosack
Keyword(s):  
High Performance ◽  
Large Scale ◽  
Recent Progress ◽  
Low Voltage ◽  
Silicon On Insulator ◽  
Significant Interest ◽  
Significant Performance ◽  
Cmos Ic ◽  
Bulk Processing ◽  
Soi Technology

Silicon-On-Insulator (SOI) technology [1-4] has been shown to have significant performance and fabrication advantages over conventional bulk processing for a wide variety of large scale CMOS IC applications. Advantages in radiation environments has generated significant interest in this technology from military and space science communities [5,6]. Possible advantages of SOI technology for low power, low voltage and high performance circuit applications is under serious consideration by several commercial IC manufacturers [7,8].

scholarly journals Optimal design of electromagnetically actuated MEMS cantilevers

2018 ◽  
Author(s):  
Paolo Di Barba ◽  
Teodor Gotszalk ◽  
Wojciech Majstrzyk ◽  
Maria Evelina Mognaschi ◽  
Karolina Orlowska ◽  
...  
Keyword(s):  
Methodological Approach ◽  
Cost Effective ◽  
Silicon On Insulator ◽  
Electromagnetic Actuation ◽  
Effective Technique ◽  
Cost Effective Technique ◽  
Sensor Properties ◽  
Mems Cantilevers ◽  
Electromagnetically Actuated ◽  
Soi Technology

In this paper we present the numerical and experimental results of a design optimization of electromagnetic cantilevers. In particular, a cost-effective technique of evolutionary computing enabling the simultaneous minimization of multiple criteria is applied. A set of optimal solutions are subsequently fabricated and measured. The designed structures are fabricated in arrays, which makes the comparison and measurements of the sensor properties reliable. The microfabrication process, based on the silicon on insulator (SOI) technology, is proposed in order to minimize parasitic phenomena and enable efficient electromagnetic actuation. Measurements on the fabricated prototypes assessed the proposed methodological approach.

scholarly journals Preparative Purification of Recombinant Proteins: Current Status and Future Trends

2013 ◽  
Vol 2013 ◽  
pp. 1-18 ◽  
Author(s):  
Mayank Saraswat ◽  
Luca Musante ◽  
Alessandra Ravidá ◽  
Brian Shortt ◽  
Barry Byrne ◽  
...  
Keyword(s):  
High Performance ◽  
Cost Effective ◽  
Downstream Processing ◽  
Current Status ◽  
Comprehensive Overview ◽  
Two Phase ◽  
Phase Partitioning ◽  
Absolute Requirement ◽  
Flow Filtration ◽  
Selection Of

Advances in fermentation technologies have resulted in the production of increased yields of proteins of economic, biopharmaceutical, and medicinal importance. Consequently, there is an absolute requirement for the development of rapid, cost-effective methodologies which facilitate the purification of such products in the absence of contaminants, such as superfluous proteins and endotoxins. Here, we provide a comprehensive overview of a selection of key purification methodologies currently being applied in both academic and industrial settings and discuss how innovative and effective protocols such as aqueous two-phase partitioning, membrane chromatography, and high-performance tangential flow filtration may be applied independently of or in conjunction with more traditional protocols for downstream processing applications.

Improved Soi Films By High Dose Oxygen Implantation and Lamp Annealing

1985 ◽  
Vol 53 ◽  
Author(s):  
G. K. Celler ◽  
P. L. F. Hemment ◽  
K. W. West ◽  
J. M. Gibson
Keyword(s):  
High Speed ◽  
Ion Beam ◽  
Silicon On Insulator ◽  
High Dose ◽  
Cmos Circuits ◽  
Radiation Hardened ◽  
Silicon On Insulator Technology ◽  
Annealing Procedure ◽  
Oxygen Precipitates ◽  
Sharp Interfaces

ABSTRACTIon beam synthesis of a buried SiO2 layer is an attractive silicon-on-insulator technology for high speed CMOS circuits and radiation hardened devices. We demonstrate here a new annealing procedure at 1405°C that produces silicon films of excellent quality, essentially free of oxygen precipitates and with sharp interfaces between the Si and the SiO2.

scholarly journals Optimal Design of Electromagnetically Actuated MEMS Cantilevers

Sensors ◽  
2018 ◽  
Vol 18 (8) ◽  
pp. 2533 ◽  
Author(s):  
Paolo Di Barba ◽  
Teodor Gotszalk ◽  
Wojciech Majstrzyk ◽  
Maria Mognaschi ◽  
Karolina Orłowska ◽  
...  
Keyword(s):  
Methodological Approach ◽  
Cost Effective ◽  
Silicon On Insulator ◽  
Electromagnetic Actuation ◽  
Effective Technique ◽  
Cost Effective Technique ◽  
Sensor Properties ◽  
Mems Cantilevers ◽  
Electromagnetically Actuated ◽  
Soi Technology

In this paper we present the numerical and experimental results of a design optimization of electromagnetic cantilevers. In particular, a cost-effective technique of evolutionary computing enabling the simultaneous minimization of multiple criteria is applied. A set of optimal solutions are subsequently fabricated and measured. The designed cantilevers are fabricated in arrays, which makes the comparison and measurements of the sensor properties reliable. The microfabrication process, based on the silicon on insulator (SOI) technology, is proposed in order to minimize parasitic phenomena and enable efficient electromagnetic actuation. Measurements on the fabricated prototypes assessed the proposed methodological approach.

Nanoprobing of Advanced Silicon-On-Insulator Transistors

2019 ◽  
Author(s):  
Stefano Larentis ◽  
Kent Erington ◽  
Jose Z. Garcia ◽  
Khiem Ly ◽  
Kris Dickson ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Case Studies ◽  
Electrical Characterization ◽  
Silicon On Insulator ◽  
New Device ◽  
Device Structures ◽  
Well Leakage ◽  
Soi Technology

Abstract As advanced silicon-on-insulator (SOI) technology becomes a more widespread technology offering, failure analysis approaches should be adapted to new device structures. We review two nanoprobing case studies of advanced SOI technology, detailing the electrical characterization of a compound gate-to-drain defect as well as the characterization of unexpected SOI source-to-well leakage.

Structural changes in silicon-on-insulator material during post-implantation annealing

1986 ◽  
Vol 44 ◽  
pp. 736-737
Author(s):  
C. O. Jung ◽  
S. J. Krause ◽  
S.R. Wilson
Keyword(s):  
Integrated Circuits ◽  
Oxide Layer ◽  
High Speed ◽  
Structural Changes ◽  
Device Fabrication ◽  
Silicon On Insulator ◽  
High Quality ◽  
Radiation Hardened ◽  
Post Implantation ◽  
Very High

Silicon-on-insulator (SOI) structures have excellent potential for future use in radiation hardened and high speed integrated circuits. For device fabrication in SOI material a high quality superficial Si layer above a buried oxide layer is required. Recently, Celler et al. reported that post-implantation annealing of oxygen implanted SOI at very high temperatures would eliminate virtually all defects and precipiates in the superficial Si layer. In this work we are reporting on the effect of three different post implantation annealing cycles on the structure of oxygen implanted SOI samples which were implanted under the same conditions.

Analysis of Silicon-On-Insulator Structures Formed By Oxygen Ion Implantation

1985 ◽  
Vol 43 ◽  
pp. 300-301
Author(s):  
N. Lewis ◽  
E. L. Hall ◽  
A. Mogro-Campero ◽  
R. P. Love
Keyword(s):  
Ion Implantation ◽  
Single Crystal ◽  
Single Crystal Silicon ◽  
Silicon Layer ◽  
Device Fabrication ◽  
Silicon On Insulator ◽  
High Dose ◽  
Crystal Silicon ◽  
Oxygen Ion ◽  
Oxygen Ion Implantation

The formation of buried oxide structures in single crystal silicon by high-dose oxygen ion implantation has received considerable attention recently for applications in advanced electronic device fabrication. This process is performed in a vacuum, and under the proper implantation conditions results in a silicon-on-insulator (SOI) structure with a top single crystal silicon layer on an amorphous silicon dioxide layer. The top Si layer has the same orientation as the silicon substrate. The quality of the outermost portion of the Si top layer is important in device fabrication since it either can be used directly to build devices, or epitaxial Si may be grown on this layer. Therefore, careful characterization of the results of the ion implantation process is essential.

Behavior of contact-silicided TFSOI gate structures

1994 ◽  
Vol 52 ◽  
pp. 860-861
Author(s):  
N. David Theodore ◽  
Juergen Foerstner ◽  
Peter Fejes
Keyword(s):  
Semiconductor Device ◽  
Series Resistance ◽  
Field Effect Transistors ◽  
Silicon Layer ◽  
Device Fabrication ◽  
Silicon On Insulator ◽  
Continuous Layer ◽  
Buried Oxide ◽  
Device Structures ◽  
Thin Silicon

As semiconductor device dimensions shrink and packing-densities rise, issues of parasitic capacitance and circuit speed become increasingly important. The use of thin-film silicon-on-insulator (TFSOI) substrates for device fabrication is being explored in order to increase switching speeds. One version of TFSOI being explored for device fabrication is SIMOX (Silicon-separation by Implanted OXygen).A buried oxide layer is created by highdose oxygen implantation into silicon wafers followed by annealing to cause coalescence of oxide regions into a continuous layer. A thin silicon layer remains above the buried oxide (~220 nm Si after additional thinning). Device structures can now be fabricated upon this thin silicon layer.Current fabrication of metal-oxidesemiconductor field-effect transistors (MOSFETs) requires formation of a polysilicon/oxide gate between source and drain regions. Contact to the source/drain and gate regions is typically made by use of TiSi2 layers followedby Al(Cu) metal lines. TiSi2 has a relatively low contact resistance and reduces the series resistance of both source/drain as well as gate regions

Defect reduction in oxygen implanted silicon-on-insulator material during high-temperature annealing

1989 ◽  
Vol 47 ◽  
pp. 604-605
Author(s):  
P. Roitman ◽  
B. Cordts ◽  
S. Visitserngtrakul ◽  
S.J. Krause
Keyword(s):  
High Temperature ◽  
Annealing Temperature ◽  
Silicon On Insulator ◽  
High Dose ◽  
High Temperature Annealing ◽  
High Current ◽  
Defect Reduction ◽  
Annealing Step ◽  
Multiple Cycle ◽  
Defect Densities

Synthesis of a thin, buried dielectric layer to form a silicon-on-insulator (SOI) material by high dose oxygen implantation (SIMOX – Separation by IMplanted Oxygen) is becoming an important technology due to the advent of high current (200 mA) oxygen implanters. Recently, reductions in defect densities from 109 cm−2 down to 107 cm−2 or less have been reported. They were achieved with a final high temperature annealing step (1300°C – 1400°C) in conjunction with: a) high temperature implantation or; b) channeling implantation or; c) multiple cycle implantation. However, the processes and conditions for reduction and elimination of precipitates and defects during high temperature annealing are not well understood. In this work we have studied the effect of annealing temperature on defect and precipitate reduction for SIMOX samples which were processed first with high temperature, high current implantation followed by high temperature annealing.

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