Experiment and Modelisation Results on Laser Thermal Processing for Ultra-Shallow Junction Formation: Influence of Laser Pulse Duration

2003 ◽  
Vol 765 ◽  
Author(s):  
J. Venturini ◽  
M. Hernandez ◽  
D. Zahorski ◽  
G. Kerrien ◽  
T. Sarnet ◽  
...  

AbstractAccording to the International Technology Roadmap for Semiconductors (ITRS), the doping technology requirements for the MOSFET source and drain regions of the future CMOS generations lead to a major challenge. A critical point of this evolution is the formation of ultra-shallow junctions(USJ) for which present technologies, based on ion implantation and rapid thermal annealing, will hardly meet the ITRS specifications. Laser Thermal Processing (LTP) has been shown to be a potential candidate to solve this fundamental problem. In the present paper, LTP experiments have been performed with two XeCl excimer lasers (λ= 308 nm) with different pulse characteristics. The first laser (Lambda Physik, Compex 102) delivers 200 mJ laser pulses with a duration of ∼25 ns. The second laser is an industrial tool (SOPRA, VEL 15) that delivers 16 J laser pulses with a duration of ∼200 ns and allows to anneal a few cm die in a single laser shot. Here we examine the influence of the pulse duration on LTP of B+ (with and without Ge+ pre-amorphization) and BF2 implanted silicon samples on the basis of real-time optical monitoring of the laser induced melting/recrystallisation process, four-point probe resistivity measurements, secondary ion mass spectrometry (SIMS) depth profiles. Experimental results are compared to finite element modelisation (FIDAP Fluent Software) that takes into account both laser pulses. The activated dopant dose, junction depth and sheet resistance, as a function of the laser fluence and shot number for both lasers, confirm the efficiency of laser processing to realize ultra-shallow and highly doped junctions as required by the future CMOS generations. Influence of the pulse duration on the USJ formation process is also discussed.

2002 ◽  
Vol 717 ◽  
Author(s):  
Erik Kuryliw ◽  
Kevin S. Jones ◽  
David Sing ◽  
Michael J. Rendon ◽  
Somit Talwar

AbstractLaser Thermal Processing (LTP) involves laser melting of an implantation induced preamorphized layer to form highly doped ultra shallow junctions in silicon. In theory, a large number of interstitials remain in the end of range (EOR) just below the laser-formed junction. There is also the possibility of quenching in point defects during the liquid phase epitaxial regrowth of the melt region. Since post processing anneals are inevitable, it is necessary to understand both the behavior of these interstitials and the nature of point defects in the recrystallized-melt region since they can directly affect deactivation and enhanced diffusion. In this study, an amorphizing 15 keV 1 x 1015/cm2 Si+ implant was done followed by a 1 keV 1 x 1014/cm2 B+ implant. The surface was then laser melted at energy densities between 0.74 and 0.9 J/cm2 using a 308 nm excimer-laser. It was found that laser energy densities above 0.81 J/cm2 melted past the amorphous-crystalline interface. Post-LTP furnace anneals were performed at 750°C for 2 and 4 hours. Transmission electron microscopy was used to analyze the defect formation after LTP and following furnace anneals. Secondary ion mass spectrometry measured the initial and final boron profiles. It was observed that increasing the laser energy density led to increased dislocation loop formation and increased diffusion after the furnace anneal. A maximum loop density and diffusion was observed at the end of the process window, suggesting a correlation between the crystallization defects and the interstitial evolution.


2008 ◽  
Author(s):  
Frank Torregrosa ◽  
Hasnaa Etienne ◽  
Guillaume Sempere ◽  
Gilles Mathieu ◽  
Laurent Roux ◽  
...  

2004 ◽  
Vol 453-454 ◽  
pp. 145-149 ◽  
Author(s):  
J. Venturini ◽  
M. Hernandez ◽  
G. Kerrien ◽  
C. Laviron ◽  
D. Camel ◽  
...  

2020 ◽  
Vol 12 (3) ◽  
pp. 189
Author(s):  
Sebastian Gäb

When we were on the subway back from his lecture, I said to Robin: “I’m not sure there actually are any religious fictionalists.” We keep talking about them in papers and lectures, acting as if fictionalism in religion is a real possibility, but to be honest, I haven’t been able to spot one in the wild so far. The only potential candidate who comes to mind is Don Cupitt, who wrote things like: “I still pray and love God, even though I fully acknowledge that no God actually exists.”[1] Perhaps this is as fictionalist as it gets. But then again, Cupitt never explicitly declared himself a fictionalist (at least to my knowledge). Moreover, on other occasions he sounds more like an expressivist than a fictionalist, e.g. when he says: “The Christian doctrine of God just is Christian spirituality in coded form.”[2] So, if there are any actual fictionalists out there, please step forward.[1] Don Cupitt, After God: The Future of Religion (Basic Books, 1997), 85.[2] Don Cupitt, Taking leave of God (SCM Press, 1980), 14.


1998 ◽  
Author(s):  
Somit Talwar ◽  
Gaurav Verma ◽  
Kurt H. Weiner ◽  
Carol Gelatos

Nanomaterials ◽  
2021 ◽  
Vol 11 (12) ◽  
pp. 3166
Author(s):  
Sayed Md Tariful Azam ◽  
Abu Saleh Md Bakibillah ◽  
Md Tanvir Hasan ◽  
Md Abdus Samad Kamal

In this study, we theoretically investigated the effect of step gate work function on the InGaAs p-TFET device, which is formed by dual material gate (DMG). We analyzed the performance parameters of the device for low power digital and analog applications based on the gate work function difference (∆ϕS-D) of the source (ϕS) and drain (ϕD) side gate electrodes. In particular, the work function of the drain (ϕD) side gate electrodes was varied with respect to the high work function of the source side gate electrode (Pt, ϕS = 5.65 eV) to produce the step gate work function. It was found that the device performance varies with the variation of gate work function difference (∆ϕS-D) due to a change in the electric field distribution, which also changes the carrier (hole) distribution of the device. We achieved low subthreshold slope (SS) and off-state current (Ioff) of 30.89 mV/dec and 0.39 pA/µm, respectively, as well as low power dissipation, when the gate work function difference (∆ϕS-D = 1.02 eV) was high. Therefore, the device can be a potential candidate for the future low power digital applications. On the other hand, high transconductance (gm), high cut-off frequency (fT), and low output conductance (gd) of the device at low gate work function difference (∆ϕS-D = 0.61 eV) make it a viable candidate for the future low power analog applications.


2012 ◽  
Vol 2012 (1) ◽  
pp. 000433-000439 ◽  
Author(s):  
Jeroen van Borkulo ◽  
Rene Hendriks ◽  
Peter Dijkstra

The traditional blade dicing technology has gone through an impressive evolution keeping up with quality, cost and miniaturization requirements that the semiconductor technology roadmaps introduced and specified. However, since wafer technologies have dropped below 90nm node and low k materials were introduced it became clear that blade dicing evolution came to an end and expensive hybrid solutions such as combined laser grooving processes and blade dicing technologies were required to achieve the desired product reliability. Similar situations have been seen with the ongoing trend to thinner wafer that are needed for miniaturization, 3D packaging and IC performance improvements. To achieve sufficient mechanical strength, complex dicing technologies and sequences have been introduced which do not respond to the requirements for current and near future technologies. This paper will discuss the low-k grooving process by laser pulses for IC wafers. The low-K laser grooving technology allows semiconductor manufacturers to execute the technology roadmap and continue to comply with Moore's law in an efficient manner. In specific this paper will elaborate on the comparison study made between the single beam and multi beam low-K grooving process. Together with a large IDM customer a comparison has been done to determine the results on quality, Heat Affected Zone (HAZ), productivity and yield.


2020 ◽  
Vol 21 (8) ◽  
pp. 2744 ◽  
Author(s):  
Adriana Kubis-Kubiak ◽  
Aleksandra Dyba ◽  
Agnieszka Piwowar

The brain is an organ in which energy metabolism occurs most intensively and glucose is an essential and dominant energy substrate. There have been many studies in recent years suggesting a close relationship between type 2 diabetes mellitus (T2DM) and Alzheimer’s disease (AD) as they have many pathophysiological features in common. The condition of hyperglycemia exposes brain cells to the detrimental effects of glucose, increasing protein glycation and is the cause of different non-psychiatric complications. Numerous observational studies show that not only hyperglycemia but also blood glucose levels near lower fasting limits (72 to 99 mg/dL) increase the incidence of AD, regardless of whether T2DM will develop in the future. As the comorbidity of these diseases and earlier development of AD in T2DM sufferers exist, new AD biomarkers are being sought for etiopathogenetic changes associated with early neurodegenerative processes as a result of carbohydrate disorders. The S100B protein seem to be interesting in this respect as it may be a potential candidate, especially important in early diagnostics of these diseases, given that it plays a role in both carbohydrate metabolism disorders and neurodegenerative processes. It is therefore necessary to clarify the relationship between the concentration of the S100B protein and glucose and insulin levels. This paper draws attention to a valuable research objective that may in the future contribute to a better diagnosis of early neurodegenerative changes, in particular in subjects with T2DM and may be a good basis for planning experiments related to this issue as well as a more detailed explanation of the relationship between the neuropathological disturbances and changes of glucose and insulin concentrations in the brain.


Author(s):  
C. Michael Garner

Because the transistor was fabricated in volume, lithography has enabled the increase in density of devices and integrated circuits. With the invention of the integrated circuit, lithography enabled the integration of higher densities of field-effect transistors through evolutionary applications of optical lithography. In 1994, the semiconductor industry determined that continuing the increase in density transistors was increasingly difficult and required coordinated development of lithography and process capabilities. It established the US National Technology Roadmap for Semiconductors and this was expanded in 1999 to the International Technology Roadmap for Semiconductors to align multiple industries to provide the complex capabilities to continue increasing the density of integrated circuits to nanometre scales. Since the 1960s, lithography has become increasingly complex with the evolution from contact printers, to steppers, pattern reduction technology at i-line, 248 nm and 193 nm wavelengths, which required dramatic improvements of mask-making technology, photolithography printing and alignment capabilities and photoresist capabilities. At the same time, pattern transfer has evolved from wet etching of features, to plasma etch and more complex etching capabilities to fabricate features that are currently 32 nm in high-volume production. To continue increasing the density of devices and interconnects, new pattern transfer technologies will be needed with options for the future including extreme ultraviolet lithography, imprint technology and directed self-assembly. While complementary metal oxide semiconductors will continue to be extended for many years, these advanced pattern transfer technologies may enable development of novel memory and logic technologies based on different physical phenomena in the future to enhance and extend information processing.


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