scholarly journals A New Systematic Encoding  Circuit of Hamming (15, 11) Using Low-Power XOR-FS-GDI Based Logic Gate: Fast Computing and Efficient Area FEC

2021 ◽  
Author(s):  
Mohsen El-Bendary ◽  
O El-Badry
Keyword(s):  
Low Power ◽  
Delay Time ◽  
Power Efficiency ◽  
Logic Gate ◽  
Logic Gates ◽  
The Other ◽  
Simulation Experiments ◽  
Hamming Codes ◽  
Communications Systems ◽  
Other Hand

Abstract Due to the power efficiency importance of digital signal processing and data protection in different communications systems, this paper proposes an efficient design of different Hamming Codes utilizing Full Swing- Gate Diffusion Input (FS-GDI) approach. The proposed codes design aims to improve the power efficiency and the required area through reducing the required number of transistors. FS-GDI is a new low power VLSI design approach, it is a power effective approach for realizing the different logic gates. In this work, the Hamming codes (11, 7) and (15, 11) are designed by utilizing the original GDI, FS-GDI and the traditional CMOS approaches. The amount of consumed power, delay time, Power Delay Product (PDP) and hardware simplicity-Number of Transistors (No. Ts) are employed as a metrics for evaluating the efficiency of the proposed design compared to the traditional design. The design simulation experiments are executed utilizing Cadence Virtuoso simulator package under 65nm technology. The simulation experiments revealed these proposed codes achieve delay time reduction by 52.91% and 10% for Hamming codes (7, 4) and (11, 7), respectively On the other hand, the Hardware (H/W) of these codes became more simple where the H/W simplicity of the used Hamming codes is reduced 50 % CMOS approaches respectively. From the results analysis, the proposed design achieves efficient power and the delay optimizing of Hamming codes utilizing the FS-GDI approach. On the other hand, the power consumption and area in communications systems due to the encoding process can be reduces.

scholarly journals Optimizing of Communications Systems Power Efficiency Considerations: Efficient Implementing Approach of Hamming Codes Utilizing FS-GDI

2021 ◽  
Author(s):  
Mohsen El-Bendary ◽  
O. El-Badry
Keyword(s):  
Delay Time ◽  
Power Efficiency ◽  
Vlsi Design ◽  
Logic Gates ◽  
The Other ◽  
Efficient Design ◽  
Simulation Experiments ◽  
Hamming Codes ◽  
Communications Systems ◽  
Other Hand

Abstract Due to the power efficiency importance of digital signal processing and data protection in different communications systems, this paper proposes an efficient design of different Hamming Codes utilizing Full Swing- Gate Diffusion Input (FS-GDI) approach. The proposed codes design aims to improve the power efficiency and the required area through reducing the required number of transistors. FS-GDI is a new low power VLSI design approach, it is a power effective approach for realizing the different logic gates. In this work, the Hamming codes (7, 4) and (11, 7) are designed by utilizing the original GDI, FS-GDI and the traditional CMOS approaches. The amount of consumed power, delay time, Power Delay Product (PDP) and hardware simplicity-Number of Transistors (No.Ts) are employed as a metrics for evaluating the efficiency of the proposed design compared to the traditional design. The design simulation experiments are executed utilizing Cadence Virtuoso simulator package under 65nm technology. The simulation experiments revealed these proposed codes achieve delay time reduction by 52.91% and 10% for Hamming codes (7, 4) and (11, 7), respectively On the other hand, the Hardware (H/W) of these codes became more simple where the H/W simplicity of the used Hamming codes is reduced 50 % CMOS approaches respectively. From the results analysis, the proposed design achieves efficient power and the delay optimizing of Hamming codes utilizing the FS-GDI approach. On the other hand, the power consumption and area in communications systems due to the encoding process can be reduces.

scholarly journals Various Nano-Scale Technologies: Lower Hardware Complexity of Alu Realizing Utilizing FS-GDI Approach IN 45nm AND 130nm

2021 ◽  
Vol 14 (1) ◽  
pp. 9-34
Author(s):  
Mohsen A. M. El-Bendary ◽  
◽  
M. Ayman ◽  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Delay Time ◽  
Digital Circuits ◽  
Logic Gates ◽  
Propagation Delay ◽  
Hardware Complexity ◽  
Simulation Experiments ◽  
Lower Power ◽  
Full Swing

Full Swing Gate Diffusion Input (FS-GDI) approach is power effective approach for realizing the different logic gates. In this research, this approach is utilized for realizing different four ALU design using 45nm and 130nm technologies. Also, the different low power VLSI logic styles and related past works are discussed with considering the 45nm and 65nm technologies for implementing various circuits for studying the technology size impact. The performance of the proposed ALU design is evaluated through power consumption, propagation delay and number of transistors. The variation of the ALU performance due to the used 45nm and 130nm technologies has been studied. The simulation is carried out utilizing Cadence Virtuoso simulator. The simulation experiments revealed the energy of the 4-bit ALU reduced by 32% compared to CMOS-based design and area of the digital circuits reducing. Regarding the different nano technologies, 45nm technology provides lower power consumption and delay time deceasing compared to ALU unit by 130nm technology. The presented approach of low hardware complexity achieves simplicity of the required ALU hardware through reducing the number of transistors.

Compact Hardware Implementations of MISTY1 Block Cipher

2017 ◽  
Vol 27 (03) ◽  
pp. 1850037 ◽  
Author(s):  
Yasir ◽  
Ning Wu ◽  
Xiaoqiang Zhang
Keyword(s):  
Low Power ◽  
Block Cipher ◽  
Comprehensive Analysis ◽  
The Other ◽  
Key Generation ◽  
Round Function ◽  
Other Hand ◽  
Hardware Implementations ◽  
Covered Area

This paper proposes compact hardware implementations of 64-bit NESSIE proposed MISTY1 block cipher for area constrained and low power ASIC applications. The architectures comprise only one round MISTY1 block cipher algorithm having optimized FO/FI function by re-utilizing S9/S7 substitution functions. A focus is also made on efficient logic implementations of S9 and S7 substitution functions using common sub-expression elimination (CSE) and parallel AND/XOR gates hierarchy. The proposed architecture 1 generates extended key with independent FI function and is suitable for MISTY1 8-rounds implementation. On the other hand, the proposed architecture 2 uses a single FO/FI function for both MISTY1 round function as well as extended key generation and can be employed for MISTY1 [Formula: see text] rounds. To analyze the performance and covered area for ASICs, Synopsys Design Complier, SMIC 0.18[Formula: see text][Formula: see text]m @ 1.8[Formula: see text]V is used. The hardware constituted 3041 and 2331 NAND gates achieving throughput of 171 and 166 Mbps for 8 rounds implementation of architectures 1 and 2, respectively. Comprehensive analysis of proposed designs is covered in this paper.

scholarly journals A Novel Design and Implementation of New Double Feynman and Six-correction logic (DFSCL) gates in Quantum-dot Cellular Automata (QCA)

2017 ◽  
Vol 13 (15) ◽  
pp. 265
Author(s):  
Sajjad Waheed ◽  
Sharmin Aktar ◽  
Ali Newaz Bahar
Keyword(s):  
Information Processing ◽  
Cellular Automata ◽  
Power Consumption ◽  
Low Power ◽  
Logic Gate ◽  
Processing System ◽  
Logic Gates ◽  
Low Power Consumption ◽  
Switching Frequency ◽  
Promising Alternative

In recent years, quantum cellular automata (QCA) have been used widely to digital circuits and systems. QCA technology is a promising alternative to CMOS technology. It is attractive due to its fast speed, small area and low power consumption. The QCA offers a novel electronics paradigm for information processing and communication. It has the potential for attractive features such as faster speed, higher scale integration, higher switching frequency, smaller size and low power consumption than transistor based technology. In this paper, Double Feynman and Six-correction logic gate (DFSCL) is proposed based on QCA logic gates: MV gate and Inverter gate. The proposed circuit is a promising future in constructing of nano-scale low power consumption information processing system and can stimulate higher digital applications in QCA.

CHARACTERIZATION, TEST AND LOGIC SYNTHESIS OF NOVEL CONSERVATIVE AND REVERSIBLE LOGIC GATES FOR QCA

2010 ◽  
Vol 09 (03) ◽  
pp. 201-214 ◽  
Author(s):  
KUNAL DAS ◽  
DEBASHIS DE
Keyword(s):  
Low Power ◽  
Large Scale ◽  
Symmetric Functions ◽  
Logic Gate ◽  
Logic Synthesis ◽  
Vlsi Design ◽  
Logic Gates ◽  
Reversible Logic ◽  
Computing Paradigm ◽  
Scale Integration

Quantum dot cellular automaton (QCA) is an emerging technology in the field of nanotechnology. Reversible logic is emerging as a promising computing paradigm with applications in low-power quantum computing and QCA in the field of very large scale integration (VLSI) design. In this paper, we worked on conservative logic gate (CLG) and reversible logic gate (RLG). We examined that RLG and CLG are two classes of logic family intersecting each other. The intersection of RLG and CLG is parity preserving reversible (PPR) or conservative reversible logic gate (CRLG). We proposed in this paper, three algorithms to find different k × k RLG as well as CLG. Here, we demonstrate only the most promising two proposed gates of different categories. We compared the results with that of the previous Fredkin gate. The result shows that logic synthesis using above two gates will be a promising step towards the low-power QCA design era. We have shown a parity preserving approach to design all possible CLG. We also discuss a coupled Majority–minority-Voter (MmV) in a single nanostructure, dual outputs are driven simultaneously. This MmV gate is used for implementing n variables symmetric functions, testing the conservative gates as we explained that parity must be preserved if Majority and Minority output are same as input as well as output of CLG.

scholarly journals Gate-All-Around FETs: Nanowire and Nanosheet Structure

2020 ◽  
Author(s):  
Jun-Sik Yoon ◽  
Jinsu Jeong ◽  
Seunghwan Lee ◽  
Junjong Lee ◽  
Rock-Hyun Baek
Keyword(s):  
Low Power ◽  
High Performance ◽  
The Other ◽  
Short Channel ◽  
Technology Node ◽  
Channel Characteristics ◽  
Other Hand ◽  
Rc Delay

DC/AC performances of 3-nm-node gate-all-around (GAA) FETs having different widths and the number of channels (Nch) from 1 to 5 were investigated thoroughly using fully-calibrated TCAD. There are two types of GAAFETs: nanowire (NW) FETs having the same width (WNW) and thickness of the channels, and nanosheet (NS) FETs having wide width (WNS) but the fixed thickness of the channels as 5 nm. Compared to FinFETs, GAAFETs can maintain good short channel characteristics as the WNW is smaller than 9 nm but irrespective of the WNS. DC performances of the GAAFETs improve as the Nch increases but at decreasing rate because of the parasitic resistances at the source/drain epi. On the other hand, gate capacitances of the GAAFETs increase constantly as the Nch increases. Therefore, the GAAFETs have minimum RC delay at the Nch near 3. For low power applications, NWFETs outperform FinFETs and NSFETs due to their excellent short channel characteristics by 2-D structural confinement. For standard and high performance applications, NSFETs outperform FinFETs and NWFETs by showing superior DC performances arising from larger effective widths per footprint. Overall, GAAFETs are great candidates to substitute FinFETs in the 3-nm technology node for all the applications.

scholarly journals Proposal of a Cascade Photonic Crystal XOR Logic Gate for Optical Integrated Circuits with Investigation of Fabrication Error and Optical Power Changes

Photonics ◽  
2021 ◽  
Vol 8 (9) ◽  
pp. 392
Author(s):  
Ahmad Mohebzadeh-Bahabady ◽  
Saeed Olyaee
Keyword(s):  
Photonic Crystal ◽  
Integrated Circuits ◽  
Low Power ◽  
Logic Gate ◽  
Contrast Ratio ◽  
Optical Power ◽  
Logic Gates ◽  
Optical Integrated Circuits ◽  
Fabrication Error ◽  
All Optical

A compact and simple structure is designed to create an all-optical XOR logic gate using a two-dimensional, photonic crystal lattice. The structure was implemented using three waveguides connected by two nano-resonators. The plane wave expansion method was used to obtain the photonic band gap and the finite-difference time-domain method was used to investigate the behavior of the electromagnetic field in the photonic crystal structure. Examining the high contrast ratio and high-speed cascade, all-optical XOR on a chip, the effects of fabrication error and the changes in the input optical power showed that the structure could be used in optical integrated circuits. The contrast ratio and data transfer rate of the cascade XOR logic gate were respectively obtained as 44.29 dB and 1.5 Tb/s. In addition, the designed structure had very small dimensions at 158.65 μm2 and required very low power to operate, which made it suitable for low-power circuits. This structure could also be used as a NOT logic gate. Therefore, an XNOR logic gate can be designed using XOR and NOT logic gates.

Low Power High Speed MISTY1 Cryptography Approaches

2018 ◽  
Vol 27 (13) ◽  
pp. 1850200 ◽  
Author(s):  
Abdoul Rjoub ◽  
Ehab M. Ghabashneh
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
High Speed ◽  
Logic Gate ◽  
Logic Gates ◽  
Portable Devices ◽  
Silicon Area ◽  
Dynamic Power ◽  
Conventional Design ◽  
Reduction Approach

The demand for high performance, low power/secured handheld equipment increased the need for high speed/low energy and efficient encryption/decryption algorithms. Recently, efficient techniques were suggested to increase the standard of security as well as the speed of portable and handheld devices. Also, those techniques cause increment in the lifetime of battery by reducing the total silicon capacitance and minimizing the switching activity. This paper presents two approaches to reduce the number of logic gates at S7 and S9 of MISTY1 in order to reduce the total delay time, power dissipation and silicon area. The Logic Gate Reduction Approach (LGRA) reduces the number of logic gates by applying Boolean Algebra rules and simplifications, while the Duplicated Gate Reduction Approach (DGRA) removes the redundant XOR and AND logic gates which form the S7 and S9 blocks ciphers. The LGRA approach shows that the throughput enhanced by 21.1% compared to the conventional design, the silicon area reduced by 26.8%, while the dynamic power dissipation is reduced by 21.7% on average. The DGRA approach shows that the throughput enhanced by 3.8% compared to the conventional design, the silicon area reduced by 31.7%, while the dynamic power dissipation is reduced by 27% on average. As a result, the proposed approaches could be fit for next generation of handheld and portable devices.

scholarly journals ORGANIC MEMRISTOR DEVICES FOR LOGIC ELEMENTS WITH MEMORY

2012 ◽  
Vol 22 (11) ◽  
pp. 1250283 ◽  
Author(s):  
VICTOR EROKHIN ◽  
GERARD DAVID HOWARD ◽  
ANDREW ADAMATZKY
Keyword(s):  
Low Power ◽  
Logic Gate ◽  
Logic Gates ◽  
Full Adder ◽  
Experimental Results ◽  
Boolean Logic ◽  
Next Generation ◽  
Nanoscale Fabrication ◽  
Thresholding Function ◽  
With Memory

Memristors are promising next-generation memory candidates that are nonvolatile, possess low power requirements and are capable of nanoscale fabrication. In this article, we physically realize and describe the use of organic memristors in designing stateful boolean logic gates for the AND OR and NOT operations. The output of these gates is analog and dependent on the length of time that suitable charge is applied to the inputs, displaying a learning property. Results may be also interpreted in a traditional binary manner through the use of a suitable thresholding function at the output. The memristive property of the gate allows for the production of analog outputs that vary based on the charge-dependent nonvolatile state of the memristor. We provide experimental results of physical fabrication of three types of logic gate. A simulation of a one-bit full adder comprised of memristive logic gates is also included, displaying varying response to two distinct input patterns.

scholarly journals Logic Gates Formed by Perturbations in an Asynchronous Game of Life

Symmetry ◽  
2021 ◽  
Vol 13 (5) ◽  
pp. 907
Author(s):  
Yoshihiko Ohzawa ◽  
Yukio-Pegio Gunji
Keyword(s):  
Logic Gate ◽  
Logic Gates ◽  
Logic Circuits ◽  
The Other ◽  
Probabilistic Logic ◽  
Two Dimensional ◽  
Game Of Life ◽  
The Subject ◽  
Logical Gate ◽  
Or Gate

The game of life (GL), a type of two-dimensional cellular automaton, has been the subject of many studies because of its simple mechanism and complex behavior. In particular, the construction of logic circuits using the GL has helped to extend the concept of computation. Conventional logic circuits assume deterministic transitions due to the synchronicity of the classic GL. However, they are fragile to noise and cannot maintain the expected behavior in an environment with noise. In this study, a probabilistic logic gate model was constructed using perturbations in an asynchronous game of life (AGL). Since our asynchronous automaton had no heterogeneity in either the horizontal or vertical directions, it was symmetrical with respect to spatial structure. On the other hand, the construction of the logical gate was implemented to contain heterogeneity in the horizontal or vertical directions, which could allow an AND gate and an OR gate in a single system. It was based on the phase transition between connected and unconnected phases, which is newly discovered in this study. In the model, perturbations symmetrically entail operations successful and unsuccessful, and this symmetrical double action is given not to interfere with established operations but to make operations possible. Therefore, this model had a different meaning from logic gates that exclude perturbations or use them externally. The idea of this perturbation is analogous to the inherent noise that destroys and generates structures in biological swarms.

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