scholarly journals A Novel Superjunction MOSFET with Ultralow Reverse Recovery Charge and Low Switching Loss

2021 ◽  
Author(s):  
Yun Xia ◽  
Wanjun Chen ◽  
Bo Zhang ◽  
Zhaoji Li
Keyword(s):  
Schottky Diode ◽  
Schottky Contact ◽  
Reverse Current ◽  
Total Power ◽  
Drift Region ◽  
Switching Loss ◽  
Field Plate ◽  
Switching Losses ◽  
Source Field ◽  
P Type

Abstract A novel superjunction MOSFET (SJ-MOSFET) for ultralow reverse recovery charge (Q RR ) and low switching loss is proposed and investigated. This device features a P-type Schottky diode and a source field-plate. The P-type Schottky diode consists of Schottky contact and P-base, which is reverse series-connected with body P-N junction diode. And the source field-plate is formed by implementing a polysilicon field-plate electrically coupled to the source, which is on the top of N-pillar. During the reverse conduction state, the P-type Schottky diode is reverse biased, which dramatically suppresses minority carriers injecting into the drift region. Simultaneously, electron accumulation layer formed under the source field-plate, which provides a path for the reverse current. Consequently, compared with the conventional SJ-MOSFET (Conv-SJ-MOSFET), the proposed SJ-MOSFET achieves an 84.0% lower Q RR with almost no sacrifice in other characteristics. Moreover, the proposed device also exhibits 47.4% and 66.0% lower gate charge (Q G ) and gate to drain charge (Q GD ), respectively. The significantly reduced Q G , Q GD , and Q RR contribute to an overall improvement in switching losses and resultant over 54.8% decrease in total power losses with operation frequency higher than 50 kHz, demonstrating great potential of the proposed SJ-MOSFET used in power conversion systems.

scholarly journals Enhanced Reverse Recovery Performance in Superjunction MOSFET with Reduced Hole-Barrier

2022 ◽  
Author(s):  
Yun Xia ◽  
wanjun Chen ◽  
Chao Liu ◽  
Ruize Sun ◽  
zhaoji Li ◽  
...  
Keyword(s):  
Power Conversion ◽  
Schottky Contact ◽  
Total Power ◽  
Drift Region ◽  
Power Losses ◽  
Switching Losses ◽  
Conduction State ◽  
Drain Side ◽  
Main Factors ◽  
Recovery Performance

Abstract High reverse recovery charge (QRR) and resultant high switching losses have become the main factors that constrain the performance and application area of superjunction MOSFET (SJ-MOSFET). To reduce QRR, an SJ-MOSFET with reduced hole-barrier is proposed and demonstrated. By introducing a Schottky contact on the bottom of the n-pillar at the drain side, the barrier for the hole carrier is dramatically reduced in the reverse conduction state. As a result, the hole carrier in the drift region is significantly reduced, which results in a low QRR and enhanced reverse recovery performance. Compared with the conventional SJ-MOSFET (Conv-SJ-MOSFET), the proposed device achieves 64.6% lower QRR with almost no sacrifice in other characteristics. The attenuated QRR accounts for a 19.6% ~ 46.8% reduction in total power losses with operation frequency at 5 ~ 200 kHz, demonstrating the great potential of the proposed SJ-MOSFET used in power conversion systems.

scholarly journals A Novel LDMOS with Ultralow Specific on-Resistance and Improved Switching Performance

2021 ◽  
Author(s):  
Lijuan Wu ◽  
Haifeng Wu ◽  
Jinsheng Zeng ◽  
Xing Chen ◽  
Shaolian Su
Keyword(s):  
Breakdown Voltage ◽  
Current Distribution ◽  
Doping Concentration ◽  
Electric Field Distribution ◽  
Drift Region ◽  
Optimal Doping ◽  
Field Plate ◽  
Switching Performance ◽  
Switching Losses ◽  
Optimal Doping Concentration

Abstract A stepped split triple-gate SOI LDMOS with P/N strip (P/N SSTG SOI LDMOS) is proposed, which has ultralow specific on-resistance (Ron,sp) and low switching losses. The proposed device has a triple-gate (TG) and stepped split gates (SSGs). P strip, N-drift and oxide trench are alternately arranged in the Z direction. Meanwhile, the SSGs are located in the oxide trench of the N-drift region and are distributed in steps. Firstly, the TG increases the channel width (Wch) and has the effect of modulating current distribution, resulting in lower Ron,sp and higher transconductance (gm). Secondly, the SSGs serve as the field plate to assist the depletion of the N-drift region, increasing the optimal doping concentration of the N-drift region (Nd-opt) and further reducing the Ron,sp. Moreover, the SSGs also have the effect of modulating the electric field distribution to maintain a high breakdown voltage (BV). Meanwhile, gate-drain charge (QGD) and switching losses are reduced on account of the introduction of the SSGs. Thirdly, in the off-state, the P strip and SSGs multidimensional assisted depletion of the N-drift region, which greatly increases the Nd-opt. The highly doped N-drift region provides a low-resistance path for the current, which also further reduces Ron,sp. Compared with triple-gate (TG) SOI LDMOS with almost equal breakdown voltage, the Ron,sp and QGD of P/N SSTG SOI LDMOS are reduced by 62% and 63%, respectively.

Simulation study for GaN-based hybrid trench MOS barrier Schottky diode with an embedded p-type NiO termination: increased forward current density and enhanced breakdown voltage

2021 ◽  
Author(s):  
Fuping Huang ◽  
Chunshuang Chu ◽  
Xingyu Jia ◽  
Kangkai Tian ◽  
Yonghui Zhang ◽  
...  
Keyword(s):  
Breakdown Voltage ◽  
Schottky Diode ◽  
Current Density ◽  
Schottky Contact ◽  
Hybrid Structure ◽  
Optimization Strategy ◽  
Energy Bands ◽  
Spreading Effect ◽  
Forward Current ◽  
P Type

Abstract In this work, a hybrid trench MOS barrier Schottky diode (TMBS) structure is proposed to improve both the forward current density and the breakdown voltage (BV) by using TCAD simulation tools. The hybrid structure means that the conventional TMBS rectifier is combined with a p-NiO/n-GaN diode. This can modulate the lateral energy bands by removing the conduction band barriers for electrons. Thus, the improved current spreading effect and the better conductivity modulation can be obtained, leading to the increased current density. Meanwhile, the embedded p-type NiO layer can also help to reduce the electric field at Schottky contact interface and the edge of anode contact/p-NiO layer interface. Thus, the breakdown voltage can be improved remarkably. Moreover, a detailed optimization strategy for the hybrid TMBS is also analyzed by varying the p-NiO layer thickness (TNiO) and the lengths of the anode electrode that is covered on the p-NiO layer (LA).

Design of a 4H-SiC RESURF n-LDMOS Transistor for High Voltage Integrated Circuits

2019 ◽  
Vol 963 ◽  
pp. 629-632
Author(s):  
Julietta Weisse ◽  
Heinz Mitlehner ◽  
Lothar Frey ◽  
Tobias Erlbacher
Keyword(s):  
Integrated Circuits ◽  
Charge Compensation ◽  
Drift Region ◽  
Cmos Process ◽  
Field Plate ◽  
Blocking Voltage ◽  
P Type ◽  
Fabrication Parameters ◽  
Channel Region ◽  
Reduced Surface

In this work, a lateral 4H-SiC n-LDMOS transistor, based on the principle of a reduced surface field due to charge compensation, is investigated by numerical simulations, in order to find adequate fabrication parameters for a lightly doped p-type epitaxy in combination with a higher doped channel region. The purpose of this work is the integration into an existing technology for a 10 V 4H-SiC-CMOS process. The simulations predict in a blocking voltage of 1.3 kV in combination with an On-resistance of 17 mΩcm2 for a device with a RESURF structure with a total implanted Al concentration of 6∙1016 cm-3 and a depth of 1 μm, a field plate of 5 μm and a drift region of 20 μm. The threshold voltage varies from 5 V to 10 V, depending on the thickness of the gate oxide (50 nm to 100 nm).

scholarly journals SiC Fin-Shaped Gate Trench MOSFET with Integrated Schottky Diode

Materials ◽  
2021 ◽  
Vol 14 (22) ◽  
pp. 7096
Author(s):  
Xiaochuan Deng ◽  
Rui Liu ◽  
Songjun Li ◽  
Ling Li ◽  
Hao Wu ◽  
...  
Keyword(s):  
Schottky Diode ◽  
High Efficiency ◽  
Physical Mechanism ◽  
Short Circuit ◽  
Dynamic Performance ◽  
Schottky Contact ◽  
Promising Candidate ◽  
Extreme Stress ◽  
P Type ◽  
Gate Charge

A silicon carbide (SiC) trench MOSFET featuring fin-shaped gate and integrated Schottky barrier diode under split P type shield (SPS) protection (FS-TMOS) is proposed by finite element modeling. The physical mechanism of FS-TMOS is studied comprehensively in terms of fundamental (blocking, conduction, and dynamic) performance and transient extreme stress reliability. The fin-shaped gate on the sidewall of the trench and integrated Schottky diode at the bottom of trench aim to the reduction of gate charge and improvement on the third quadrant performance, respectively. The SPS region is fully utilized to suppress excessive electric field both at trench oxide and Schottky contact when OFF-state. Compared with conventional trench MOSFET (C-TMOS), the gate charge, Miller charge, Von at third quadrant, Ron,sp·Qgd, and Ron,sp·Qg of FS-TMOS are significantly reduced by 34%, 20%, 65%, 0.1%, and 14%, respectively. Furthermore, short-circuit and avalanche capabilities are discussed, verifying the FS-TMOS is more robust than C-TMOS. It suggests that the proposed FS-TMOS is a promising candidate for next-generation high efficiency and high-power density applications.

Simulation of p-type Schottky Diode Based on Al0.29Ga0.71As with Titanium/Gold Schottky Contact

2018 ◽  
Author(s):  
Walid Filali ◽  
Slimane Oussalah ◽  
Noureddine Sengouga ◽  
Mohamed Henini ◽  
David Taylor
Keyword(s):  
Schottky Diode ◽  
Schottky Contact ◽  
P Type

Comparison of Current – Voltage Characteristics of N and P Type 6H-SiC Schottky Diodes

2000 ◽  
Vol 640 ◽  
Author(s):  
Q. Zhang ◽  
V. Madangarli ◽  
Y. Gao ◽  
T. S. Sudarshan
Keyword(s):  
Schottky Diode ◽  
Room Temperature ◽  
Voltage Drop ◽  
Schottky Diodes ◽  
Reverse Current ◽  
Turn On ◽  
Current Voltage ◽  
Forward Voltage Drop ◽  
P Type ◽  
State Resistance

ABSTRACTForward and reverse current – voltage (I–V) characteristics of N and P-type Schottky diodes on 6H-SiC are compared in a temperature range of room temperature to 550K. While the room temperature I–V characteristics of the N-type Schottky diode after turn-on is more or less linear up to ∼ 100 A/cm2, the I–V characteristics of the P-type Schottky diode shows a non-linear behavior even after turn-on, indicating a variation in the on-state resistance with increase in forward current. For the first time it is shown that at high current densities (> 210 A/cm2) the forward voltage drop across P type Schottky diodes is lower than that across N type Schottky diodes on 6H-SiC. High temperature measurements indicate that while the on-state resistance of N type Schottky diodes increases with increase in temperature, the on-state resistance of P type Schottky diodes decreases with increase in temperature until a certain temperature. While the N-type diodes seem to have soft breakdown characteristics, the P-type diodes exhibit more or less abrupt breakdown characteristics.

Temperature-Dependent Characteristics of 4H-SiC Buried Grid JBS Diodes

2015 ◽  
Vol 821-823 ◽  
pp. 600-603 ◽  
Author(s):  
Jang Kwon Lim ◽  
S.A. Reshanov ◽  
Wlodek Kaplan ◽  
A. Zhang ◽  
Tomas Hjort ◽  
...  
Keyword(s):  
Leakage Current ◽  
Doping Concentration ◽  
Voltage Drop ◽  
Schottky Contact ◽  
Drift Region ◽  
Forward Voltage ◽  
Forward Voltage Drop ◽  
Increasing Temperature ◽  
P Type ◽  
State Resistance

4H-SiC Schottky Barrier Diodes (SBD) have been developed using p-type buried grids (BGs) formed by Al implantation. In order to reduce on-state resistance and improve forward conduction, the doping concentration of the channel region between the buried grids was increased. The fabricated diodes were encapsulated with TO-254 packages and electrically evaluated. Experimental forward and reverse characteristics were measured in the temperature range from 25 °C to 250 °C. On bare die level, the forward voltage drop was reduced from 5.36 V to 3.90 V at 20 A as the channel doping concentration was increased, which introduced a low channel resistance. By the encapsulation in TO-254 package, the forward voltage drop was decreased approximately 10% due to a lower contact resistance. The on-state resistance of the identical device measured on bare die and in TO-254 package increased with increasing temperature due to the decreased electron mobility in the drift region resulting in higher resistance. The incremental contact resistances of the bare dies were larger than in the packaged devices. One key issue associated with conventional Junction Barrier Schottky (JBS) diodes is a high leakage current at high temperature operation over 200 °C. The developed Buried Grid JBS (BG JBS) diode has significantly reduced leakage current due to a better field shielding at the Schottky contact. The leakage current of the packaged BG JBS diodes is compared to pure SBD and commercial JBS diodes.

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