Design of a 4H-SiC RESURF n-LDMOS Transistor for High Voltage Integrated Circuits

In this work, a lateral 4H-SiC n-LDMOS transistor, based on the principle of a reduced surface field due to charge compensation, is investigated by numerical simulations, in order to find adequate fabrication parameters for a lightly doped p-type epitaxy in combination with a higher doped channel region. The purpose of this work is the integration into an existing technology for a 10 V 4H-SiC-CMOS process. The simulations predict in a blocking voltage of 1.3 kV in combination with an On-resistance of 17 mΩcm2 for a device with a RESURF structure with a total implanted Al concentration of 6∙1016 cm-3 and a depth of 1 μm, a field plate of 5 μm and a drift region of 20 μm. The threshold voltage varies from 5 V to 10 V, depending on the thickness of the gate oxide (50 nm to 100 nm).

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12 kV 4H-SiC p-IGBTs with Record Low Specific On-Resistance

Materials Science Forum ◽

10.4028/www.scientific.net/msf.600-603.1187 ◽

2008 ◽

Vol 600-603 ◽

pp. 1187-1190 ◽

Cited By ~ 22

Author(s):

Q. Jon Zhang ◽

Charlotte Jonas ◽

Joseph J. Sumakeris ◽

Anant K. Agarwal ◽

John W. Palmour

Keyword(s):

Carrier Lifetime ◽

Drift Region ◽

Gate Bias ◽

Enhancement Layer ◽

Channel Mobility ◽

Dc Characteristics ◽

Blocking Voltage ◽

High Carrier ◽

P Type ◽

First Time

DC characteristics of 4H-SiC p-channel IGBTs capable of blocking -12 kV and conducting -0.4 A (-100 A/cm2) at a forward voltage of -5.2 V at 25°C are demonstrated for the first time. A record low differential on-resistance of 14 mW×cm2 was achieved with a gate bias of -20 V indicating a strong conductivity modulation in the p-type drift region. A moderately doped current enhancement layer grown on the lightly doped drift layer effectively reduces the JFET resistance while maintains a high carrier lifetime for conductivity modulation. A hole MOS channel mobility of 12.5 cm2/V-s at -20 V of gate bias was measured with a MOS threshold voltage of -5.8 V. The blocking voltage of -12 kV was achieved by Junction Termination Extension (JTE).

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New High-Voltage Unipolar Mode p+ Si/n– 4H-SiC Heterojunction Diode

Materials Science Forum ◽

10.4028/www.scientific.net/msf.483-485.953 ◽

2005 ◽

Vol 483-485 ◽

pp. 953-956 ◽

Cited By ~ 12

Author(s):

Tetsuya Hayashi ◽

Hideaki Tanaka ◽

Yoshio Shimoida ◽

Satoshi Tanimoto ◽

Masakatsu Hoshi

Keyword(s):

Leakage Current ◽

High Voltage ◽

Drift Region ◽

Heterojunction Diode ◽

Inductive Load ◽

Low Leakage ◽

Low Leakage Current ◽

Blocking Voltage ◽

Switching Characteristics ◽

P Type

We demonstrate a new high-voltage p+ Si/n- 4H-SiC heterojunction diode (HJD) by numerical simulation and experimental results. This HJD is expected to display good reverse recovery because of unipolar action similar to that of a SiC Schottky barrier diode (SBD) when forward biased. The blocking voltage of the HJD is almost equal to the ideal level in the drift region of n- 4H-SiC. In addition, the HJD has the potential for a lower reverse leakage current compared with the SBD. A HJD was fabricated with p+-type polycrystalline silicon on an n--type epitaxial layer of 4H-SiC. Measured reverse blocking voltage was 1600 V with low leakage current. Switching characteristics of the fabricated HJD showed nearly zero reverse recovery with an inductive load circuit.

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DC Characteristics Optimization of a Double G-Shield 50 V RF LDMOS

Advances in Condensed Matter Physics ◽

10.1155/2015/379746 ◽

2015 ◽

Vol 2015 ◽

pp. 1-7

Author(s):

Xiangming Xu ◽

Pengliang Ci ◽

Xiaoyu Tang ◽

Jing Shi ◽

Zhengliang Zhou ◽

...

Keyword(s):

Dopant Concentration ◽

Measurement Data ◽

Drift Region ◽

Junction Depth ◽

Obvious Effect ◽

Field Plate ◽

Dc Characteristics ◽

Simulation Results ◽

Tcad Simulation ◽

Reduced Surface

An N-type 50 V RF LDMOS with a RESURF (reduced surface field) structure of dual field plates (grounded shield, or G-shield) was investigated. The effect of the two field plates and N-drift region, including the junction depth and dopant concentration, on the DC characteristics was analyzed by employing the Taurus TCAD device simulator. A high BV (breakdown voltage) can be achieved while keeping a lowRDSON(on-resistance). The simulation results show that the N-drift region dopant concentration has an obvious effect on the BV andRDSONand the junction depth affected these values less. There is an optimized length for the second field plate for a given dopant concentration of the N-drift region. Both factors should be optimized together to determine the best DC characteristics. Meanwhile, the effect of the first field plate on the BV andRDSONcan be ignored. According to the simulation results, 50 V RF LDMOS with an optimized RESURF structure of a double G-shield was fabricated using 0.35 µm technologies. The measurement data show the same trend as the TCAD simulation, where a BV of 118 V andRDSONof 26 ohm·mm were achieved.

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A Novel Superjunction MOSFET with Ultralow Reverse Recovery Charge and Low Switching Loss

10.21203/rs.3.rs-347647/v1 ◽

2021 ◽

Author(s):

Yun Xia ◽

Wanjun Chen ◽

Bo Zhang ◽

Zhaoji Li

Keyword(s):

Schottky Diode ◽

Schottky Contact ◽

Reverse Current ◽

Total Power ◽

Drift Region ◽

Switching Loss ◽

Field Plate ◽

Switching Losses ◽

Source Field ◽

P Type

Abstract A novel superjunction MOSFET (SJ-MOSFET) for ultralow reverse recovery charge (Q RR ) and low switching loss is proposed and investigated. This device features a P-type Schottky diode and a source field-plate. The P-type Schottky diode consists of Schottky contact and P-base, which is reverse series-connected with body P-N junction diode. And the source field-plate is formed by implementing a polysilicon field-plate electrically coupled to the source, which is on the top of N-pillar. During the reverse conduction state, the P-type Schottky diode is reverse biased, which dramatically suppresses minority carriers injecting into the drift region. Simultaneously, electron accumulation layer formed under the source field-plate, which provides a path for the reverse current. Consequently, compared with the conventional SJ-MOSFET (Conv-SJ-MOSFET), the proposed SJ-MOSFET achieves an 84.0% lower Q RR with almost no sacrifice in other characteristics. Moreover, the proposed device also exhibits 47.4% and 66.0% lower gate charge (Q G ) and gate to drain charge (Q GD ), respectively. The significantly reduced Q G , Q GD , and Q RR contribute to an overall improvement in switching losses and resultant over 54.8% decrease in total power losses with operation frequency higher than 50 kHz, demonstrating great potential of the proposed SJ-MOSFET used in power conversion systems.

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Interface morphology of thermal oxide grown on polycrystalline silicon by different processes

Proceedings, annual meeting, Electron Microscopy Society of America ◽

10.1017/s0424820100131619 ◽

1992 ◽

Vol 50 (2) ◽

pp. 1396-1397

Author(s):

H. Yen ◽

E. P. Kvam ◽

R. Bashir ◽

S. Venkatesan ◽

G. W. Neudeck

Keyword(s):

Integrated Circuits ◽

Polycrystalline Silicon ◽

Silicon Films ◽

Interface Morphology ◽

Oxide Interface ◽

Poly Silicon ◽

Thermal Oxide ◽

Grain Orientations ◽

Polycrystalline Silicon Films ◽

P Type

Polycrystalline silicon, when highly doped, is commonly used in microelectronics applications such as gates and interconnects. The packing density of integrated circuits can be enhanced by fabricating multilevel polycrystalline silicon films separated by insulating SiO2 layers. It has been found that device performance and electrical properties are strongly affected by the interface morphology between polycrystalline silicon and SiO2. As a thermal oxide layer is grown, the poly silicon is consumed, and there is a volume expansion of the oxide relative to the atomic silicon. Roughness at the poly silicon/thermal oxide interface can be severely deleterious due to stresses induced by the volume change during oxidation. Further, grain orientations and grain boundaries may alter oxidation kinetics, which will also affect roughness, and thus stress.Three groups of polycrystalline silicon films were deposited by LPCVD after growing thermal oxide on p-type wafers. The films were doped with phosphorus or arsenic by three different methods.

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Timing Sensitivity Analysis of Logical Nodes in Scan Design Integrated Circuits by Pulsed Diode Laser Stimulation

ISTFA 2008: Conference Proceedings from the 34th International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2008p0180 ◽

2008 ◽

Author(s):

T. Kiyan ◽

C. Boit ◽

C. Brillert

Keyword(s):

Laser Pulse ◽

Integrated Circuits ◽

Continuous Wave ◽

Fault Injection ◽

Scan Design ◽

Flip Flop ◽

Laser Stimulation ◽

Scan Chain ◽

P Type ◽

Scan Pattern

Abstract In this paper, a methodology based upon laser stimulation and a comparison of continuous wave and pulsed laser operation will be presented that localizes the fault relevant sites in a fully functional scan chain cell. The technique uses a laser incident from the backside to inject soft faults into internal nodes of a master-slave scan flip-flop in consequence of localized photocurrent. Depending on the illuminated type of the transistors (n- or p-type), injection of a logic ‘0’ or ‘1’ into the master or the slave stage of a flip-flop takes place. The laser pulse is externally triggered and can easily be shifted to various time slots in reference to clock and scan pattern. This feature of the laser diode allows triggering the laser pulse on the rising or the falling edge of the clock. Therefore, it is possible to choose the stage of the flip-flop in which the fault injection should occur. It is also demonstrated that the technique is able to identify the most sensitive signal condition for fault injection with a better time resolution than the pulse width of the laser, a significant improvement for failure analysis of integrated circuits.

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Ground Plane Impact on Performance of Relaxed Ge FinFETs

Journal of Integrated Circuits and Systems ◽

10.29292/jics.v14i1.55 ◽

2019 ◽

Vol 14 (1) ◽

pp. 1-6

Author(s):

Alberto Vinícius Oliveira ◽

Guilherme Vieira Gonçalves ◽

Paula Ghedini Der Agopian ◽

João Antonio Martino ◽

Jérôme Mitard ◽

...

Keyword(s):

Threshold Voltage ◽

Computer Aided Design ◽

Doping Concentration ◽

Ground Plane ◽

Subthreshold Swing ◽

Voltage Variation ◽

Electrostatic Coupling ◽

P Type ◽

Aided Design ◽

Channel Region

The implementation of a barrier potential layer underneath the channel region, well known as Ground Plane (GP) implantation, and its influence on the performance of relaxed germanium pFinFET devices is investigated in this manuscript. This study aims to explain the fin width dependence of the threshold voltage from experimental data and evaluates the ground plane doping concentration and its depth influence on relaxed p-type channel germanium FinFET parameters, as threshold voltage, transconductance and subthreshold swing, through Technology Computer-Aided Design (TCAD) numerical simulations. The threshold voltage variation reaches up to 80 mV from the narrowest device to the widest one, considering the studied range of ground plane doping concentration. Concerning the subthreshold swing parameter, neither the GP doping concentration, nor its depth play a significant role since the electrostatic coupling is predominant.

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Extended High-Temperature Operation of Silicon Carbide CMOS Circuits for Venus Surface Application

Journal of Microelectronics and Electronic Packaging ◽

10.4071/imaps.527 ◽

2016 ◽

Vol 13 (4) ◽

pp. 143-154 ◽

Cited By ~ 4

Author(s):

Jim Holmes ◽

A. Matthew Francis ◽

Ian Getreu ◽

Matthew Barlow ◽

Affan Abbasi ◽

...

Keyword(s):

High Temperature ◽

Integrated Circuits ◽

Integrated Circuit ◽

Field Effect ◽

Field Effect Transistors ◽

Logic Synthesis ◽

Oxide Semiconductor ◽

Cmos Process ◽

Timing Models ◽

High Temperature Operation

In the last decade, significant effort has been expended toward the development of reliable, high-temperature integrated circuits. Designs based on a variety of active semiconductor devices including junction field-effect transistors and metal-oxide-semiconductor (MOS) field-effect transistors have been pursued and demonstrated. More recently, advances in low-power complementary MOS (CMOS) devices have enabled the development of highly integrated digital, analog, and mixed-signal integrated circuits. The results of elevated temperature testing (as high as 500°C) of several building block circuits for extended periods (up to 100 h) are presented. These designs, created using the Raytheon UK's HiTSiC® CMOS process, present the densest, lowest-power integrated circuit technology capable of operating at extreme temperatures for any period. Based on these results, Venus nominal temperature (470°C) transistor models and gate-level timing models were created using parasitic extracted simulations. The complete CMOS digital gate library is suitable for logic synthesis and lays the foundation for complex integrated circuits, such as a microcontroller. A 16-bit microcontroller, based on the OpenMSP 16-bit core, is demonstrated through physical design and simulation in SiC-CMOS, with an eye for Venus as well as terrestrial applications.

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Practical Design of 4H-SiC Superjunction Devices in the Presence of Charge Imbalance

Materials Science Forum ◽

10.4028/www.scientific.net/msf.924.563 ◽

2018 ◽

Vol 924 ◽

pp. 563-567

Author(s):

Md Monzurul Alam ◽

Dallas T. Morisette ◽

James A. Cooper

Keyword(s):

Drift Region ◽

Charge Balance ◽

Ideal Case ◽

Charge Imbalance ◽

Blocking Voltage ◽

Practical Design ◽

Proper Design ◽

Improved Performance ◽

The Relationship ◽

The Ideal

In the ideal case, superjunction (SJ) drift regions theoretically exhibit a linear relationship between specific-on resistance Ron,sp and blocking voltage VBR, but this requires perfect charge balance between the alternating n and p pillars. If any degree of imbalance exists, the relationship becomes quadratic, similar to a conventional drift region, although with somewhat improved performance. In this work, we analyze superjunction drift regions in 4H-SiC under realistic degrees of charge imbalance and show that, with proper design, a reduction in specific on-resistance of 2~10x is possible as long as the imbalance remains less than ±20%.

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