scholarly journals Advantageous Sampling of Correlated Current Signals to Supress Fixed-Pattern Noise in CMOS Imagers

2017 ◽  
Vol 12 (1) ◽  
pp. 47-55
Author(s):  
R. A. Souza ◽  
L. G. M. Ventura ◽  
A. R. S. Martins ◽  
D. W. de Lima Monteiro ◽  
L. P. Salles
Keyword(s):  
Integrated Circuit ◽  
Supply Voltage ◽  
Process Variations ◽  
Current Mode ◽  
Physical Parameters ◽  
Basic Operation ◽  
Silicon Area ◽  
Cmos Imagers ◽  
Pattern Noise ◽  
Fixed Pattern Noise

The Active Pixel Sensor (APS) has been a vastly used integrated circuit topology in CMOS imagers. Mismatch of physical parameters among pixels, caused by process variations, introduces Fixed-Pattern Noise (FPN) at the array output. Correlated Double Sampling (CDS) in voltage mode is a commonly used method to suppress the offset caused FPN. However, it increases the complexity as well as the demanded silicon area of either the pixel or the external circuitry, besides having its signal swing restricted by the supply voltage. An alternative CDS circuit operating in current mode to reduce FPN is presented in this paper. The correlated current signals are sampled and subtracted using a simpler circuitry, leading to a more efficient relation of FPN reduction for the required silicon area. Furthermore, this technique does not change the APS topology or basic operation cycle. A simulated and tested CDS alternative is presented, and a simulated further improved version is proposed. Simulation and experiments showed a 40% FPN reduction with the fabricated CDS, whereas the improved simulated version ensures 90% FPN reduction.

scholarly journals Design of area-efficient GHz range current mode frequency synthesizer using standard CMOS technology

2019 ◽  
Vol 70 (4) ◽  
pp. 323-328
Author(s):  
Dan-Dan Zheng ◽  
Yu-Bin Li ◽  
Chang-Qi Wang ◽  
Kai Huang ◽  
Xiao-Peng Yu
Keyword(s):  
Frequency Synthesizer ◽  
Frequency Tuning ◽  
Supply Voltage ◽  
Current Mode ◽  
Cmos Technology ◽  
Mode Frequency ◽  
Loop Filter ◽  
Silicon Area ◽  
Power Efficient ◽  
A Current

Abstract In this paper, an area and power efficient current mode frequency synthesizer for system-on-chip (SoC) is proposed. A current-mode transformer loop filter suitable for low supply voltage is implemented to remove the need of a large capacitor in the loop filter, and a current controlled oscillator with additional voltage based frequency tuning mechanism is designed with an active inductor. The proposed design is further integrated with a fully programmable frequency divider to maintain a good balance among output frequency operating range, power consumption as well as silicon area. A test chip is implemented in a standard 0.13 µm CMOS technology, measurement result demonstrates that the proposed design has a working range from 916 MHz to 1.1 l GHz and occupies a silicon area of 0.25 mm2 while consuming 8.4 mW from a 1.2 V supply.

A CMOS Self-Bias CTAT Current Generator with Improved Supply Sensitivity

2019 ◽  
Vol 28 (13) ◽  
pp. 1950226
Author(s):  
R. Nagulapalli
Keyword(s):  
Power Supply ◽  
Supply Voltage ◽  
Current Mode ◽  
Absolute Temperature ◽  
Loop Gain ◽  
Power Supply Voltage ◽  
Silicon Area ◽  
Simple Modification ◽  
Self Bias ◽  
Additional Circuitry

The role of complimentary to absolute temperature (CTAT) circuit in current mode bandgap has been described. Loop-gain problems with the existing self-bias MOS-based CTAT generator were discussed. A simple modification to the existing circuit was proposed to enhance the loop-gain by [Formula: see text]20[Formula: see text]dB without adding additional circuitry leading to zero additional power consumption. Power Supply Rejection and sensitivity to [Formula: see text] will be improved due to the higher loop-gain. A prototype has been developed to demonstrate the proposal robustness across PVT corners. Simulation results show 20.5[Formula: see text]dB PSRR improvement and 7.5% improvement in sensitivity to [Formula: see text]. The proposed solution consumes 180[Formula: see text]nW power from 1[Formula: see text]V power supply voltage and occupies 3300[Formula: see text][Formula: see text]m2 silicon area.

Current Mode Image Sensor With Improved Linearity and Fixed-Pattern Noise

2014 ◽  
Vol 61 (6) ◽  
pp. 1666-1674 ◽  
Author(s):  
Xiaotie Wu ◽  
Xilin Liu ◽  
Milin Zhang ◽  
Jan Van der Spiegel
Keyword(s):  
Current Mode ◽  
Image Sensor ◽  
Pattern Noise ◽  
Fixed Pattern Noise

scholarly journals Analysis and Comparison of Rad-Hard Ring and LC-Tank Controlled Oscillators in 65 nm for SpaceFibre Applications

Sensors ◽  
2020 ◽  
Vol 20 (16) ◽  
pp. 4612 ◽  
Author(s):  
Danilo Monda ◽  
Gabriele Ciarpi ◽  
Sergio Saponara
Keyword(s):  
Supply Voltage ◽  
Process Variations ◽  
Current Mode ◽  
Cmos Technology ◽  
Operating Conditions ◽  
Ring Oscillator ◽  
Space Applications ◽  
Technology Scaling ◽  
Voltage Controlled Oscillators ◽  
Lc Tank

This work presented a comparison between two Voltage Controlled Oscillators (VCOs) designed in 65 nm CMOS technology. The first architecture based on a Ring Oscillator (RO) was designed using three Current Mode Logic (CML) stages connected in a loop, while the second one was based on an LC-tank resonator. This analysis aimed to choose a VCO architecture able to be integrated into a rad-hard Phase Locked Loop. It had to meet the requirements of the SpaceFibre protocol, which supports frequencies up to 6.25 GHz, for space applications. The full custom schematic and layout designs are shown, and Single Event Effect simulations results, performed with a double exponential current pulses generator, are presented in detail for both VCOs. Although the RO-VCO performances in terms of technology scaling and high-integration density were attractive, the simulations on the process variations demonstrated its inability to generate the target frequency in harsh operating conditions. Instead, the LC-VCO highlighted a lower influence through Process-Voltage-Temperature simulations on the oscillation frequency. Both architectures were biased with a supply voltage of 1.2 V. The achieved results for the second architecture analyzed were attractive to address the requirements of the new SpaceFibre aerospace standard.

scholarly journals Multipurpose Bio-Monitored Integrated Circuit in a Contact Lens Eye-Tracker

Sensors ◽  
2022 ◽  
Vol 22 (2) ◽  
pp. 595
Author(s):  
Loïc Massin ◽  
Cyril Lahuec ◽  
Fabrice Seguin ◽  
Vincent Nourrit ◽  
Jean-Louis de Bougrenet de la Tocnaye
Keyword(s):  
Contact Lens ◽  
Integrated Circuit ◽  
Supply Voltage ◽  
Operating Time ◽  
Complementary Metal Oxide Semiconductor ◽  
Process Variations ◽  
Oxide Semiconductor ◽  
Gaze Direction ◽  
Eye Tracker ◽  
The Gaze

We present the design, fabrication, and test of a multipurpose integrated circuit (Application Specific Integrated Circuit) in AMS 0.35 µm Complementary Metal Oxide Semiconductor technology. This circuit is embedded in a scleral contact lens, combined with photodiodes enabling the gaze direction detection when illuminated and wirelessly powered by an eyewear. The gaze direction is determined by means of a centroid computation from the measured photocurrents. The ASIC is used simultaneously to detect specific eye blinking sequences to validate target designations, for instance. Experimental measurements and validation are performed on a scleral contact lens prototype integrating four infrared photodiodes, mounted on a mock-up eyeball, and combined with an artificial eyelid. The eye-tracker has an accuracy of 0.2°, i.e., 2.5 times better than current mobile video-based eye-trackers, and is robust with respect to process variations, operating time, and supply voltage. Variations of the computed gaze direction transmitted to the eyewear, when the eyelid moves, are detected and can be interpreted as commands based on blink duration or using blinks alternation on both eyes.

Enhancement in Retention Time of 3TDRAM Using Double Gate Finfet Technology at Nanometer Regime.

2021 ◽  
pp. 359-370
Author(s):  
Amol S. Sankpala, D. J. Peteb
Keyword(s):  
Leakage Current ◽  
Retention Time ◽  
Integrated Circuit ◽  
Supply Voltage ◽  
Average Power ◽  
Random Access ◽  
Cmos Technology ◽  
Double Gate ◽  
Silicon Area ◽  
Nanometer Regime

Leakage current, power and area is the key challenges for VLSI designer during implementation of low power devices. In an integrated circuit number of transistors double in small silicon area every two years. There are certain limitations of cmos technology in nanometer regime out of which leakage current, leakage power, average current and average power is an important issues. In this paper, Retention time improvement in three transistor dynamic random access memory using double gate Finfet technology is proposed. Double gate finfet technology in 3TDRAM overcomes the issues related to cmos technology and it does not required additional circuitry. Proposed 3T DRAM is investigated with cmos and finfet technology at 90nm technology using cadence tool. Analysis of 3TDRAM using cmos and double gate finfet technology is carried out by variation in supply voltage and capacitance values. In double gate finfet technology leakage parameters are minimized and retention time(Th) is more improved as compared to cmos technology is observed.

New readout integrated circuit using continuous time fixed pattern noise correction

2008 ◽  
Author(s):  
Bertrand Dupont ◽  
G. Chammings ◽  
G. Rapellin ◽  
C. Mandier ◽  
M. Tchagaspanian ◽  
...  
Keyword(s):  
Integrated Circuit ◽  
Continuous Time ◽  
Readout Integrated Circuit ◽  
Pattern Noise ◽  
Fixed Pattern Noise ◽  
Noise Correction

scholarly journals RF Transceiver for the Multi-Mode Radar Applications

Sensors ◽  
2021 ◽  
Vol 21 (5) ◽  
pp. 1563
Author(s):  
Jae Kwon Ha ◽  
Chang Kyun Noh ◽  
Jin Seop Lee ◽  
Ho Jin Kang ◽  
Yu Min Kim ◽  
...  
Keyword(s):  
Long Range ◽  
Integrated Circuit ◽  
Flicker Noise ◽  
Noise Figure ◽  
Supply Voltage ◽  
Doppler Frequency ◽  
Cmos Process ◽  
Rf Transceiver ◽  
Dc Offset ◽  
Multi Mode

In this work, a multi-mode radar transceiver supporting pulse, FMCW and CW modes was designed as an integrated circuit. The radars mainly detect the targets move by using the Doppler frequency which is significantly affected by flicker noise of the receiver from several Hz to several kHz. Due to this flicker noise, the long-range detection performance of the radars is greatly reduced, and the accuracy of range to the target and velocity is also deteriorated. Therefore, we propose a transmitter that suppresses LO leakage in consideration of long-range detection, target distance, velocity, and noise figure. We also propose a receiver structure that suppresses DC offset due to image signal and LO leakage. The design was conducted with TSMC 65 nm CMOS process, and the designed and fabricated circuit consumes a current of 265 mA at 1.2 V supply voltage. The proposed transmitter confirms the LO leakage suppression of 37 dB at 24 GHz. The proposed receiver improves the noise figure by about 20 dB at 100 Hz by applying a double conversion architecture and an image rejection, and it illustrates a DC rejection of 30 dB. Afterwards, the operation of the pulse, FMCW, and CW modes of the designed radar in integrated circuit was confirmed through experiment using a test PCB.

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