Doping Mapping by SSRM–Reaching Maturity and Sub-10nm Resolution

Author(s):  
Stephan Schömann ◽  
David Álvarez

Abstract For years there has been a discrepancy between the importance of complex doping implantation schemes for advanced technology device performance and the ability to accurately measure the carrier concentrations with the gap widening at each technology node. With scanning spreading resistance Microscopy (SSRM) a major step forward in terms of resolution and quantification was achieved especially since the emergence of full diamond tip manufacturability and improvements in sample preparation techniques. This article discusses the non-trivial prerequisites for this success and some examples from the failure analysis routine that show the promising capabilities of SSRM. The examples include technology monitoring and failure analysis in SOI transistors and vertical surrounded gate transistors, as well as failure analysis on yield and performance issues. SSRM has reached a development stage that allows its application as routine tool for 2D-carrier profiling.

Author(s):  
Ng Sea Chooi ◽  
Chor Theam Hock ◽  
Ma Choo Thye ◽  
Khoo Poh Tshin ◽  
Dan Bockelman

Abstract Trends in the packaging of semiconductors are towards miniaturization and high functionality. The package-on-package(PoP) with increasing demands is beneficial in cost and space saving. The main failure mechanisms associated with PoP technology, including open joints and warpage, have created a lot of challenges for Assembly and Failure Analysis (FA). This paper outlines the sample preparation process steps to overcome the challenges to enable successful failure analysis and optical probing.


Author(s):  
Jason H. Lagar ◽  
Rudolf A. Sia

Abstract Most Wafer Level Chip Scale Package (WLCSP) units returned by customers for failure analysis are mounted on PCB modules with an epoxy underfill coating. The biggest challenge in failure analysis is the sample preparation to remove the WLCSP device from the PCB without inducing any mechanical defect. This includes the removal of the underfill material to enable further electrical verification and fault isolation analysis. This paper discusses the evaluations conducted in establishing the WLCSP demounting process and removal of the epoxy underfill coating. Combinations of different sample preparation techniques and physical failure analysis steps were evaluated. The established process enabled the electrical verification, fault isolation and further destructive analysis of WLCSP customer returns mounted on PCB and with an epoxy underfill coating material. This paper will also showcase some actual full failure analysis of WLCSP customer returns where the established process played a vital role in finding the failure mechanism.


1997 ◽  
Vol 3 (S2) ◽  
pp. 357-358
Author(s):  
C. Amy Hunt

The demand for TEM analysis in semiconductor failure analysis is rising sharply due to the shrinking size of devices. A well-prepared sample is a necessity for getting meaningful results. In the past decades, a significant amount of effort has been invested in improving sample preparation techniques for TEM specimens, especially precision cross-sectioning techniques. The most common methods of preparation are mechanical dimpling & ion milling, focused ion beam milling (FIBXTEM), and wedge mechanical polishing. Each precision XTEM technique has important advantages and limitations that must be considered for each sample.The concept for both dimpling & ion milling and wedge specimen preparation techniques is similar. Both techniques utilize mechanical polishing to remove the majority of the unwanted material, followed by ion milling to assist in final polishing or cleaning. Dimpling & ion milling produces the highest quality samples and is a relatively easy technique to master.


Author(s):  
Axel Born ◽  
R. Wiesendanger

Abstract This paper provides guidance and insights on the use of scanning capacitance microscopy (SCM) in semiconductor failure analysis. It explains why SCM systems are constrained by rigid performance tradeoffs and how CV measurements are affected by large stray capacitance and as well as edge effects associated with the 3D geometry of the sample and probe. It also explains how samples should be prepared and how proper sample preparation techniques combined with optimally selected voltages make it possible to accurately determine doping concentrations, even in p-n junctions.


1998 ◽  
Vol 523 ◽  
Author(s):  
C. Amy Hunt ◽  
Yuhong Zhang ◽  
David Su

AbstractTransmission electron microscopy (TEM) is a useful tool in process evaluation and failure analysis for semiconductor industries. A common focus of semiconductor TEM analyses is metalization vias (plugs) and it is often desirable to cross-section through a particular one. If the cross-sectional plane deviates away from the center of the plug, then the thin adhesion layer around the plug will be blurred by surrounding materials such as the inter-layer dielectric and the plug material. The importance of these constraints, along with the difficulty of precision sample preparation, has risen sharply as feature sizes have fallen to 0.25 μm and below. The suitability of common sample preparation techniques for these samples is evaluated.


Author(s):  
Lihong Cao ◽  
Loc Tran ◽  
Wallace Donna

Abstract This article describes how Focused Ion Beam (FIB) milling methodology enhances the capability of package-level failure analysis on flip-chip packages by eliminating the artifacts induced by using conventional mechanical techniques. Dual- Beam Focused Ion Beam (DB FIB) cross sections were successful in detecting failure mechanisms related either to the die/C4 bump or package defect inside the organic substrate. This paper outlines detailed sample preparation techniques prior to performing the DB FIB cross-sections, along with case studies of DB FIB cross-sections.


Author(s):  
Seth Prejean ◽  
Victoria Bruce ◽  
Joyce Burke

Abstract This paper is about a sample preparation technique that is based on a previous research publication1. The technique was initially used for the investigation of salicide formation for CMOS process development. The initial results were very good and proved to be helpful with root cause failure analysis. Once the technique proved to be a viable failure analysis (FA) tool, a research team was formed to continue the development. This paper is written in conjunction with this team. The team is presently focused on developing a repeatable and reliable methodology of deprocessing CMOS devices from the backside. The team is also developing a methodology for post deprocessing analysis once the backside silicon is removed. The research that is presented here focuses on packaged as well as unpackaged devices. Etch rates and selectivity of tetramethylammoniumhydroxide (TMAH) is investigated along with temperature dependencies. Package material and chemical interference issues were discovered and remedied with special preparation techniques. Post deprocessing analysis is considered and many ideas are proposed as part of future research.


Author(s):  
Earl R. Walter ◽  
Glen H. Bryant

With the development of soft, film forming latexes for use in paints and other coatings applications, it became desirable to develop new methods of sample preparation for latex particle size distribution studies with the electron microscope. Conventional latex sample preparation techniques were inadequate due to the pronounced tendency of these new soft latex particles to distort, flatten and fuse on the substrate when they dried. In order to avoid these complications and obtain electron micrographs of undistorted latex particles of soft resins, a freeze-dry, cold shadowing technique was developed. The method has now been used in our laboratory on a routine basis for several years.The cold shadowing is done in a specially constructed vacuum system, having a conventional mechanical fore pump and oil diffusion pump supplying vacuum. The system incorporates bellows type high vacuum valves to permit a prepump cycle and opening of the shadowing chamber without shutting down the oil diffusion pump. A baffeled sorption trap isolates the shadowing chamber from the pumps.


Author(s):  
P. B. Basham ◽  
H. L. Tsai

The use of transmission electron microscopy (TEM) to support process development of advanced microelectronic devices is often challenged by a large amount of samples submitted from wafer fabrication areas and specific-spot analysis. Improving the TEM sample preparation techniques for a fast turnaround time is critical in order to provide a timely support for customers and improve the utilization of TEM. For the specific-area sample preparation, a technique which can be easily prepared with the least amount of effort is preferred. For these reasons, we have developed several techniques which have greatly facilitated the TEM sample preparation.For specific-area analysis, the use of a copper grid with a small hole is found to be very useful. With this small-hole grid technique, TEM sample preparation can be proceeded by well-established conventional methods. The sample is first polished to the area of interest, which is then carefully positioned inside the hole. This polished side is placed against the grid by epoxy Fig. 1 is an optical image of a TEM cross-section after dimpling to light transmission.


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