Case Studies of IR Based Rapid PC Motherboard Failure Analysis

2002 ◽  
Author(s):  
Jan Swart ◽  
John Woo ◽  
Randall Zumwalt ◽  
Jeff Birdsley ◽  
Yitages Taffese
Keyword(s):  
Integrated Circuits ◽  
Failure Analysis ◽  
End Of Life ◽  
Case Studies ◽  
Discovery Process ◽  
Ir Thermography ◽  
Ir Camera ◽  
Manufacturing Defects ◽  
Time Consumption ◽  
Functional Components

Abstract This article discusses the techniques useful in the failure discovery process in PC motherboard. It discusses the application of infrared (IR) camera in failure analysis, which overcomes time consumption problems. The article focuses on the experience gained from nine different case studies, where IR thermography system was used to both measure relative temperatures as well as absolute temperatures of components. The failures investigated are overdriven components, finding end-of-life but still functional components, correctly specified components with quality defects, incorrect component placement, internal voltage common collector to ground low resistance integrated circuits failures, PCB defects resulting in power to ground failures, soldering defects resulting in lead opens or solder bridges, and copper trace manufacturing defects or stress-induced cracks.

Combine Micro-Probing and OBIRCH to Catch Non-Recognizable Fault in RF and Mixed-Mode Integrated Circuits

2007 ◽  
Author(s):  
Cha-Ming Shen ◽  
Yen-Long Chang ◽  
Lian-Fon Wen ◽  
Tan-Chen Chuang ◽  
Shi-Chen Lin ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Radio Frequency ◽  
Failure Analysis ◽  
Case Studies ◽  
Mixed Mode ◽  
Failure Mechanisms ◽  
Deep Submicron ◽  
Digital Logic ◽  
Successful Approach ◽  
Cmos Processes

Abstract Highly-integrated radio frequency and mixed-mode devices that are manufactured in deep-submicron or more advanced CMOS processes are becoming more complex to analyze. The increased complexity presents us with many eccentric failure mechanisms that are uniquely different from traditional failure mechanisms found during failure analysis on digital logic applications. This paper presents a novel methodology to overcome the difficulties and discusses two case studies which demonstrate the application of the methodology. Through the case studies, the methodology was proven to be a successful approach. It is also proved how this methodology would work for such non-recognizable failures.

Laser Voltage Imaging: New Perspective Using Second Harmonic Detection on Submicron Technology

2012 ◽  
Author(s):  
Guillaume Celi ◽  
Sylvain Dudit ◽  
Thierry Parrassin ◽  
Michel Vallet ◽  
Philippe Perdu ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Failure Analysis ◽  
Case Studies ◽  
Second Harmonic ◽  
New Approach ◽  
Voltage Imaging ◽  
Signal Degradation ◽  
New Perspective ◽  
Process Issue ◽  
The Impact

Abstract The Laser Voltage Imaging (LVI) technique [1], introduced in 2009, appears as a very promising approach for Failure Analysis application which allows mapping frequencies through the backside of integrated circuits. In this paper, we propose a new range of application based on the study of the LVI second harmonic for signal degradation analysis. After a theoretical study of the impact of signal degradation on the second harmonic, we will demonstrate the interest of this new approach on two case studies on ultimate technology (28nm). This technique is a new approach of failure analysis that maps timing degradation and duty cycle degradation. In order to confirm the degradations we will use the LVP Technique. The last part is two real case studies on which this LVI second harmonic technique was used to find the root cause of a 28nm process issue.

Laser Voltage Probing in Failure Analysis of Advanced Integrated Circuits on SOI

2012 ◽  
Author(s):  
V.K. Ravikumar ◽  
R. Wampler ◽  
M.Y. Ho ◽  
J. Christensen ◽  
S.L. Phoa
Keyword(s):  
Integrated Circuits ◽  
Failure Analysis ◽  
Case Studies ◽  
Timing Analysis ◽  
Fault Isolation ◽  
Root Cause ◽  
Root Cause Identification

Abstract Laser voltage probing is the newest generation of tools that perform timing analysis for electrical fault isolation in advanced failure analysis facilities. This paper uses failure analysis case studies on SOI to showcase the implementation of laser voltage probing in the failure analysis flow and highlight its significance in root-cause identification.

Adaptive Grinding and Polishing of Silicon Integrated Circuits to Ultra-Thin Remaining Thickness

2015 ◽  
Author(s):  
Robert Chivas ◽  
Scott Silverman ◽  
Michael DiBattista
Keyword(s):  
Integrated Circuits ◽  
Failure Analysis ◽  
End Of Life ◽  
Surface Damage ◽  
Active Device ◽  
Analysis Techniques ◽  
Silicon Integrated Circuits ◽  
One Step ◽  
Silicon Thickness ◽  
Test Package

Abstract Anticipating the end of life for IR-based failure analysis techniques, a method of global backside preparation to ultra-thin remaining silicon thickness (RST) has been developed. Ultra-thin RST enables VIS light techniques such as laser voltage probing. In this work we investigate the lower RST limit due to sub-surface damage from grinding and a one-step polishing method to achieve 3 um RST (+/- 0.8 um) over 121 mm2 die (11 x 11 mm) test package as well as 5 um (+/- ) over 109.2 mm2 (8.0 x 13.7mm) active device.

Failure Analysis With the Scanning Electron Microscope

1972 ◽  
Vol 30 ◽  
pp. 482-483
Author(s):  
John R. Devaney
Keyword(s):  
Electron Microscope ◽  
Scanning Electron Microscope ◽  
Integrated Circuits ◽  
Failure Analysis ◽  
High Reliability ◽  
Military Applications ◽  
Small Structure ◽  
Useful Life ◽  
Insight Into ◽  
Scanning Electron

Occasionally in history, an event may occur which has a profound influence on a technology. Such an event occurred when the scanning electron microscope became commercially available to industry in the mid 60's. Semiconductors were being increasingly used in high-reliability space and military applications both because of their small volume but, also, because of their inherent reliability. However, they did fail, both early in life and sometimes in middle or old age. Why they failed and how to prevent failure or prolong “useful life” was a worry which resulted in a blossoming of sophisticated failure analysis laboratories across the country. By 1966, the ability to build small structure integrated circuits was forging well ahead of techniques available to dissect and analyze these same failures. The arrival of the scanning electron microscope gave these analysts a new insight into failure mechanisms.

Dysphagia in Hospice Care: The Roles of Social Work and Speech-Language Pathologists

2014 ◽  
Vol 23 (4) ◽  
pp. 173-186 ◽  
Author(s):  
Deborah Hinson ◽  
Aaron J. Goldsmith ◽  
Joseph Murray
Keyword(s):  
Social Work ◽  
End Of Life ◽  
Case Studies ◽  
End Of Life Care ◽  
Hospice Care ◽  
Patient Communication ◽  
Life Care ◽  
Speech Language Pathologists ◽  
Four Levels

This article addresses the unique roles of social work and speech-language pathologists (SLPs) in end-of-life and hospice care settings. The four levels of hospice care are explained. Suggested social work and SLP interventions for end-of-life nutrition and approaches to patient communication are offered. Case studies are used to illustrate the specialized roles that social work and SLP have in end-of-life care settings.

ATE Failure Isolation Methodologies for Failure Analysis, Design Debug and Yield Enhancement

1998 ◽  
Author(s):  
D.S. Patrick ◽  
L.C. Wagner ◽  
P.T. Nguyen
Keyword(s):  
Integrated Circuits ◽  
Failure Analysis ◽  
Yield Enhancement ◽  
Production Test ◽  
Final Test ◽  
Critical Design ◽  
The Past ◽  
Product Engineering ◽  
Time Savings ◽  
Analysis Design

Abstract Failure isolation and debug of CMOS integrated circuits over the past several years has become increasingly difficult to perform on standard failure analysis functional testers. Due to the increase in pin counts, clock speeds, increased complexity and the large number of power supply pins on current ICS, smaller and less equipped testers are often unable to test these newer devices. To reduce the time of analysis and improve the failure isolation capabilities for failing ICS, failure isolation is now performed using the same production testers used in product development, multiprobe and final test. With these production testers, the test hardware, program and pattern sets are already available and ready for use. By using a special interface that docks the production test head to failure isolation equipment such as the emission microscope, liquid crystal station and E-Beam prober, the analyst can quickly and easily isolate the faillure on an IC. This also enables engineers in design, product engineering and the waferfab yield enhancement groups to utilize this equipment to quickly solve critical design and yield issues. Significant cycle time savings have been achieved with the migration to this method of electrical stimulation for failure isolation.

Detection and Characterization of an Electrical Failure Induced during Laser Ablation of Packages

2008 ◽  
Author(s):  
P. Schwindenhammer ◽  
H. Murray ◽  
P. Descamps ◽  
P. Poirier
Keyword(s):  
Laser Ablation ◽  
Integrated Circuits ◽  
Failure Analysis ◽  
Ablation Process ◽  
Thermally Induced ◽  
Electrical Failure ◽  
Electrical Phenomenon ◽  
Semiconductor Packages ◽  
Complex Semiconductor

Abstract Decapsulation of complex semiconductor packages for failure analysis is enhanced by laser ablation. If lasers are potentially dangerous for Integrated Circuits (IC) surface they also generate a thermal elevation of the package during the ablation process. During measurement of this temperature it was observed another and unexpected electrical phenomenon in the IC induced by laser. It is demonstrated that this new phenomenon is not thermally induced and occurs under certain ablation conditions.

Laser Failure Isolation Techniques Demonstrated On Test Structures

2008 ◽  
Author(s):  
Frank S. Arnold
Keyword(s):  
Integrated Circuits ◽  
Laser Beam ◽  
Case Studies ◽  
Induced Resistance ◽  
Simple Test ◽  
Resistance Change ◽  
Cross Sectional ◽  
Beam Focusing ◽  
Isolation Techniques ◽  
Heating Effects

Abstract To be better prepared to use laser based failure isolation techniques on field failures of complex integrated circuits, simple test structures without any failures can be used to study Optical Beam Induced Resistance Change (OBIRCH) results. In this article, four case studies are presented on the following test structures: metal strap, contact string, VIA string, and comb test structure. Several experiments were done to investigate why an OBIRCH image was seen in certain areas of a VIA string and not in others. One experiment showed the OBRICH variation was not related to the cooling and heating effects of the topology, or laser beam focusing. A 4 point probe resistance measurement and cross-sectional views correlated with the OBIRCH results and proved OBIRCH was able to detect a variation in VIA fabrication.

Case Studies of Brittle Interfacial Failures in Area Array Solder Interconnects

2000 ◽  
Author(s):  
George M. Wenger ◽  
Richard J. Coyle ◽  
Patrick P. Solan ◽  
John K. Dorey ◽  
Courtney V. Dodd ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Case Studies ◽  
Failure Modes ◽  
Electroless Nickel ◽  
Electrical Performance ◽  
Printed Wiring Board ◽  
Solder Interconnects ◽  
Area Array ◽  
Surface Finishes ◽  
Soldering Reaction

Abstract A common pad finish on area array (BGA or CSP) packages and printed wiring board (PWB) substrates is Ni/Au, using either electrolytic or electroless deposition processes. Although both Ni/Au processes provide flat, solderable surface finishes, there are an increasing number of applications of the electroless nickel/immersion gold (ENi/IAu) surface finish in response to requirements for increased density and electrical performance. This increasing usage continues despite mounting evidence that Ni/Au causes or contributes to catastrophic, brittle, interfacial solder joint fractures. These brittle, interfacial fractures occur early in service or can be generated under a variety of laboratory testing conditions including thermal cycling (premature failures), isothermal aging (high temperature storage), and mechanical testing. There are major initiatives by electronics industry consortia as well as research by individual companies to eliminate these fracture phenomena. Despite these efforts, interfacial fractures associated with Ni/Au surface finishes continue to be reported and specific failure mechanisms and root cause of these failures remains under investigation. Failure analysis techniques and methodologies are crucial to advancing the understanding of these phenomena. In this study, the scope of the fracture problem is illustrated using three failure analysis case studies of brittle interfacial fractures in area array solder interconnects. Two distinct failure modes are associated with Ni/Au surface finishes. In both modes, the fracture surfaces appear to be relatively flat with little evidence of plastic deformation. Detailed metallography, scanning electron microscopy (SEM), energy dispersive x-ray analysis (EDX), and an understanding of the metallurgy of the soldering reaction are required to avoid misinterpreting the failure modes.

Sign in / Sign up

Export Citation Format

Share Document