3D Tomography Analysis of Dark Voltage Contrast Failure in PCRAM Device

Author(s):  
Jangwon Oh ◽  
Jonghyeop Kim ◽  
Taekwon Lee ◽  
Seungjoon Jeon ◽  
Won Kim ◽  
...  

Abstract The failure analysis using transmission electron microscopy (TEM) has been actively preceded in semiconductor industry. But due to the overlap issue and structural complexity of devices, it has become harder and harder to perform failure analysis using normal projected bright field (BF) and high angle annular dark field (HAADF) TEM images. To overcome these problems, 3-dimensional (3D) tomography technique has been suggested. In this work, we clarify the root cause of dark voltage contrast (DVC) failure at the bottom electrode contact region in PCRAM by using 3D tomography analysis. The 3D tomography samples were prepared in lamella shape by using focused ion beam (FIB). The electron energy loss spectroscopy (EELS) and 3D tomography analysis in scanning transmission electron microscope (STEM) HAADF mode were carried out. Through 3D tomography image reconstruction by AMIRA program, we observed ‘open contact fail’ between the BEC (Bottom Electrode Contact)-1 and the BEC (Bottom Electrode Contact)-2 at DVC region that could not be shown in 2D image.

Author(s):  
M.K. Dawood ◽  
C. Chen ◽  
P.K. Tan ◽  
S. James ◽  
P.S. Limin ◽  
...  

Abstract In this work, we present two case studies on the utilization of advanced nanoprobing on 20nm logic devices at contact layer to identify the root cause of scan logic failures. In both cases, conventional failure analysis followed by inspection of passive voltage contrast (PVC) failed to identify any abnormality in the devices. Technology advancement makes identifying failure mechanisms increasingly more challenging using conventional methods of physical failure analysis (PFA). Almost all PFA cases for 20nm technology node devices and beyond require Transmission Electron Microscopy (TEM) analysis. Before TEM analysis can be performed, fault isolation is required to correctly determine the precise failing location. Isolated transistor probing was performed on the suspected logic NMOS and PMOS transistors to identify the failing transistors for TEM analysis. In this paper, nanoprobing was used to isolate the failing transistor of a logic cell. Nanoprobing revealed anomalies between the drain and bulk junction which was found to be due to contact gouging of different severities.


Author(s):  
Julien Goxe ◽  
Béatrice Vanhuffel ◽  
Marie Castignolles ◽  
Thomas Zirilli

Abstract Passive Voltage Contrast (PVC) in a Scanning Electron Microscope (SEM) or a Focused Ion Beam (FIB) is a key Failure Analysis (FA) technique to highlight a leaky gate. The introduction of Silicon On Insulator (SOI) substrate in our recent automotive analog mixed-signal technology highlighted a new challenge: the Bottom Oxide (BOX) layer, by isolating the Silicon Active Area from the bulk made PVC technique less effective in finding leaky MOSFET gates. A solution involving sample preparation performed with standard FA toolset is proposed to enhance PVC on SOI substrate.


Author(s):  
X. Yang ◽  
X. Song

Abstract Novel Focused Ion Beam (FIB) voltage-contrast technique combined with TEM has been used in this study to identify a certain subtle defect mechanism that caused reliability stress failures of a new product. The suspected defect was first isolated to a unique via along the row through electrical testing and layout analysis. Static voltage contrast of FIB cross-section was used to confirm the suspected open defect at the via. Precision Transmission Electron Microscope (TEM) was then used to reveal the detail of the defect. Based on the result, proper process changes were implemented. The failure mode was successfully eliminated and the reliability of the product was greatly improved.


1998 ◽  
Vol 523 ◽  
Author(s):  
John Mardinly ◽  
David W. Susnitzky

AbstractThe demand for increasingly higher performance semiconductor products has stimulated the semiconductor industry to respond by producing devices with increasingly complex circuitry, more transistors in less space, more layers of metal, dielectric and interconnects, more interfaces, and a manufacturing process with nearly 1,000 steps. As all device features are shrunk in the quest for higher performance, the role of Transmission Electron Microscopy as a characterization tool takes on a continually increasing importance over older, lower-resolution characterization tools, such as SEM. The Ångstrom scale imaging resolution and nanometer scale chemical analysis and diffraction resolution provided by modem TEM's are particularly well suited for solving materials problems encountered during research, development, production engineering, reliability testing, and failure analysis. A critical enabling technology for the application of TEM to semiconductor based products as the feature size shrinks below a quarter micron is advances in specimen preparation. The traditional 1,000Å thick specimen will be unsatisfactory in a growing number of applications. It can be shown using a simple geometrical model, that the thickness of TEM specimens must shrink as the square root of the feature size reduction. Moreover, the center-targeting of these specimens must improve so that the centertargeting error shrinks linearly with the feature size reduction. To meet these challenges, control of the specimen preparation process will require a new generation of polishing and ion milling tools that make use of high resolution imaging to control the ion milling process. In addition, as the TEM specimen thickness shrinks, the thickness of surface amorphization produced must also be reduced. Gallium focused ion beam systems can produce hundreds of Ångstroms of amorphised surface silicon, an amount which can consume an entire thin specimen. This limitation to FIB milling requires a method of removal of amorphised material that leaves no artifact in the remaining material.


Author(s):  
Fritz Christian Awitan ◽  
Camille Joyce Garcia ◽  
Dirk Andrew Doyle ◽  
Lawrence Benedict

Abstract An ARC solution that can be used to improve backside imaging for backside photoemission microscopy applications is presented in this paper. Zinc Oxide (ZnO) -based thin films used as ARCs are deposited at the backside of the failing units through a simple and low cost spray pyrolysis technique. An improvised set-up, composed of an atomizer and a hot plate, is used in the experiment. The paper provides evidence of acceptable process repeatability and demonstrates that the technique and the material have important applications in the field of failure analysis. Furthermore, it shows that the application of ARC resulted in better defect localization. The location of the defect is easily been determined upon doing frontside inspection - to - backside image comparison on the deposited unit. By using high kV ion beam passive voltage contrast (PVC) and angled cut focused ion beam (FIB) cross section, we are able to isolate further and show the nature of the defect at the failing block.


Author(s):  
Liang Hong ◽  
Jia Li ◽  
Haifeng Wang

Abstract This paper provides an innovative root cause failure analysis method that combines multiple failure analysis (FA) techniques to narrow down and expose the shorting location and allow the material analysis of the shorting defect. It begins with a basic electrical testing to narrow down shorting metal layers, then utilizing mechanical lapping to expose over coat layers. This is followed by optical beam induced resistance change imaging to further narrow down the shorting location. Scanning electron microscopy and optical imaging are used together with focused ion beam milling to slice and view through the potential shorting area until the shorting defect is exposed. Finally, transmission electron microscopy (TEM) sample is prepared, and TEM analysis is carried out to pin point the root cause of the shorting. This method has been demonstrated successfully on Western Digital inter-metal layers shorting FA.


Author(s):  
Q. Liu ◽  
H.B. Kor ◽  
Y.W. Siah ◽  
C.L. Gan

Abstract Dual-beam focused ion beam (DB-FIB) system is widely used in the semiconductor industry to prepare cross-sections and transmission electron microscopy (TEM) lamellae, modify semiconductor devices and verify layout. One of the factors that limits its success rate is sample charging, which is caused by a lack of conductive path to discharge the accumulated charges. In this paper, an approach using an insitu micromanipulator was investigated to alleviate the charging effects. With this approach, a simple front side semiconductor device modification was carried out and the corresponding stage current was monitored to correlate to the milling process.


Author(s):  
Yu Hsiang Shu ◽  
Vincent Huang ◽  
Chia Hsing Chao

Abstract Using nanoprobing techniques to accomplish transistor parametric data has been reported as a method of failure analysis in nanometer scale defect. In this paper, we focus on how to identify the influence of Contact high resistance on device soft failures using nanoprobing analysis, and showing that the equivalent mathematical models could be used to describe the corresponding electrical data in a device with Contact high resistance issue. A case study was presented to verify that Contact volcano defect caused Contact high resistance issue, and this issue can be identified via physical failure analysis (PFA) method (e.g. Transmission Electron Microscope and Focus Ion Beam techniques) and nanoprobing analysis method. Finally, we would explain the physical root cause of Contact volcano issue.


Sign in / Sign up

Export Citation Format

Share Document