A Study on a Low Cost Thin Film Antireflection Coating Solution for Failure Analysis Applications

2016 ◽  
Author(s):  
Fritz Christian Awitan ◽  
Camille Joyce Garcia ◽  
Dirk Andrew Doyle ◽  
Lawrence Benedict
Keyword(s):  
Failure Analysis ◽  
Focused Ion Beam ◽  
Spray Pyrolysis Technique ◽  
Low Cost ◽  
Ion Beam ◽  
Antireflection Coating ◽  
Hot Plate ◽  
Coating Solution ◽  
Set Up ◽  
Voltage Contrast

Abstract An ARC solution that can be used to improve backside imaging for backside photoemission microscopy applications is presented in this paper. Zinc Oxide (ZnO) -based thin films used as ARCs are deposited at the backside of the failing units through a simple and low cost spray pyrolysis technique. An improvised set-up, composed of an atomizer and a hot plate, is used in the experiment. The paper provides evidence of acceptable process repeatability and demonstrates that the technique and the material have important applications in the field of failure analysis. Furthermore, it shows that the application of ARC resulted in better defect localization. The location of the defect is easily been determined upon doing frontside inspection - to - backside image comparison on the deposited unit. By using high kV ion beam passive voltage contrast (PVC) and angled cut focused ion beam (FIB) cross section, we are able to isolate further and show the nature of the defect at the failing block.

Solving the Voltage Contrast on Floating Substrate with Standard FA Toolset

2016 ◽  
Author(s):  
Julien Goxe ◽  
Béatrice Vanhuffel ◽  
Marie Castignolles ◽  
Thomas Zirilli
Keyword(s):  
Electron Microscope ◽  
Scanning Electron Microscope ◽  
Sample Preparation ◽  
Failure Analysis ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Silicon On Insulator ◽  
Mixed Signal ◽  
Voltage Contrast ◽  
Scanning Electron

Abstract Passive Voltage Contrast (PVC) in a Scanning Electron Microscope (SEM) or a Focused Ion Beam (FIB) is a key Failure Analysis (FA) technique to highlight a leaky gate. The introduction of Silicon On Insulator (SOI) substrate in our recent automotive analog mixed-signal technology highlighted a new challenge: the Bottom Oxide (BOX) layer, by isolating the Silicon Active Area from the bulk made PVC technique less effective in finding leaky MOSFET gates. A solution involving sample preparation performed with standard FA toolset is proposed to enhance PVC on SOI substrate.

Voltage Contrast Application on 1M SRAM Single Bit Failure Analysis

1997 ◽  
Author(s):  
D. Luo ◽  
X. Song
Keyword(s):  
Failure Analysis ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Random Access ◽  
Access Memory ◽  
Operating Life ◽  
New Techniques ◽  
Analysis Techniques ◽  
Temperature Operating ◽  
Voltage Contrast

Abstract A single bit failure is the most common and the most difficult failure mode to analyze in a Static Random Access Memory (SRAM). As chip feature sizes decrease, the difficulties compound. Traditional failure analysis techniques are often ineffective, particularly for high temperature operating life (HTOL) failures, because HTOL failures are most often caused by subtle physical defects. A new analysis approach, using Focused Ion Beam (FIB) cross-sectioning combined with Fffi passive voltage contrast (PVC), greatly enhances the analysis success rate. In this paper, we outline the use of these new techniques and apply them to a technologically important problem.

Failure Analysis of DRAM Storage Node Trench Capacitors for 0.35-Micron and Follow-On Technologies Using the Focused Ion Beam for Electrical and Physical Analysis

1996 ◽  
Author(s):  
G. Benstetter ◽  
G. Bomberger ◽  
P. Coutu ◽  
R. Danyew ◽  
R. Douse
Keyword(s):  
High Resolution ◽  
Failure Analysis ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Substrate Material ◽  
Mechanical Polishing ◽  
Physical Analysis ◽  
Storage Node ◽  
Wet Chemical ◽  
Voltage Contrast

Abstract Reducing the cell size of DRAMs in 0.35 micron and follow-on technologies requires failure analysis techniques that can analyze single storage node trench capacitors on both test sites and actual product. A combination of electrical microprobing, probeless voltage contrast and physical delayering procedures, all based on focused- ion-beam (FIB) techniques, are described. Because of precise fail localization, high resolution scanning electron microscope (SEM) imaging enables the distinction between process defects and intrinsic breakdowns of node dielectric defects. Isolated storage cells can be electrically characterized by depositing small probe pads, using FIB for contact hole milling and probe-pad deposition. To localize trench capacitors with a leakage path to the surrounding substrate, the trenches are isolated by mechanical polishing and probeless voltage contrast in the FIB tool. Failing trench capacitors can be marked in the FIB tool. Physical isolation of leaking trench capacitors can be achieved by recessing the adjacent trench capacitors, with the FIB used for milling and a subsequent wet chemical removal added for the remaining substrate material. Alternatively, trench capacitors can be inspected from the backside when stabilized by a quartz deposition on top, followed by mechanical polishing from the side and a wet chemical etching of the remaining substrate material. In both cases, the dielectric of the node trench capacitors can be inspected by high resolution SEMs and the defect areas precisely analyzed.

Failure Analysis Using Voltage Contrast and Ebic

1998 ◽  
Vol 523 ◽  
Author(s):  
Larry Rice ◽  
Wei Chen
Keyword(s):  
Electron Microscopy ◽  
Failure Analysis ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Sem Analysis ◽  
Silicon On Insulator ◽  
Traditional Use ◽  
Critical Dimensions ◽  
Voltage Contrast ◽  
Microscopy Techniques

AbstractAs ULSI device critical dimensions continue to shrink to submicron sizes, electron microscopy techniques such as electron beam induced current (EBIC) and voltage contrast are finding more applications towards pinpointing failure sites for subsequent cross sectioning or deprocessing. In addition to the traditional use of EBIC for junction delineation, EBIC has been applied to locate leakage sites in capacitor structures and silicon-on-insulator (SOI) devices as well. Similarly, voltage contrast has been applied to identify single or multiple opens in via chains which consist of thousands of vias. In addition to a brief revisit of the basic principles of EBIC and voltage contrast, focus will be placed on the application of EBIC and voltage contrast in failure analysis of semiconductor devices. Examples of using voltage contrast combined with precision cross section focused ion beam (XFIB) for identifying the failure mechanism of 0.8μm vias will be presented. Also, the use of EBIC for identifying leakage sites in SOI and bipolar devices and subsequent FIB/scanning electron microscopy (SEM) analysis will be presented.

scholarly journals Failure Analysis of a Half-Micron CMOS IC Technology

1996 ◽  
Author(s):  
A.Y. Liang ◽  
P. Tangyunyong ◽  
R.S. Bennett ◽  
R.S. Flores ◽  
J.M. Soden ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Photon Emission ◽  
Deposition Process ◽  
Cmos Technology ◽  
Contrast Imaging ◽  
Wafer Processing ◽  
Voltage Contrast ◽  
Tools And Techniques

Abstract We present the results of recent failure analysis of an advanced, 0.5 um, fully planarized, triple metallization CMOS technology. A variety of failure analysis (FA) tools and techniques were used to localize and identify defects generated by wafer processing. These include light (photon) emission microscopy (LE), fluorescent microthermal imaging (FMI), focused ion beam cross sectioning, SEM/voltage contrast imaging, resistive contrast imaging (RCI), and e-beam testing using an IDS-5000 with an HP 82000. The defects identified included inter- and intra-metal shorts, gate oxide shorts due to plasma processing damage, and high contact resistance due to the contact etch and deposition process. Root causes of these defects were determined and corrective action was taken to improve yield and reliability.

Analysis of Voltage Contrast in Secondary Electron Images Using a High-Energy Electron Spectrometer

2019 ◽  
Author(s):  
Natsuko Asano ◽  
Shunsuke Asahina ◽  
Natasha Erdman
Keyword(s):  
Focused Ion Beam ◽  
Ion Beam ◽  
Sample Surface ◽  
High Energy ◽  
Secondary Electrons ◽  
Analysis Technique ◽  
Quantitative Understanding ◽  
Voltage Contrast ◽  
Acceleration Voltage ◽  
Failure Localization

Abstract Voltage contrast (VC) observation using a scanning electron microscope (SEM) or a focused ion beam (FIB) is a common failure analysis technique for semiconductor devices.[1] The VC information allows understanding of failure localization issues. In general, VC images are acquired using secondary electrons (SEs) from a sample surface at an acceleration voltage of 0.8–2.0 kV in SEM. In this study, we aimed to find an optimized electron energy range for VC acquisition using Auger electron spectroscopy (AES) for quantitative understanding.

Direct Plan View FIB Liftout for Near-Surface Defect Analysis in TEM

2013 ◽  
Author(s):  
Max L. Lifson ◽  
Carla M. Chapman ◽  
D. Philip Pokrinchak ◽  
Phyllis J. Campbell ◽  
Greg S. Chrisman ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Silicon Germanium ◽  
Focused Ion Beam ◽  
Surface Defects ◽  
Ion Beam ◽  
Misfit Dislocations ◽  
Tem Analysis ◽  
Plan View ◽  
Near Surface ◽  
Straightforward Method

Abstract Plan view TEM imaging is a powerful technique for failure analysis and semiconductor process characterization. Sample preparation for near-surface defects requires additional care, as the surface of the sample needs to be protected to avoid unintentionally induced damage. This paper demonstrates a straightforward method to create plan view samples in a dual beam focused ion beam (FIB) for TEM studies of near-surface defects, such as misfit dislocations in heteroepitaxial growths. Results show that misfit dislocations are easily imaged in bright-field TEM and STEM for silicon-germanium epitaxial growth. Since FIB tools are ubiquitous in semiconductor failure analysis labs today, the plan view method presented provides a quick to implement, fast, consistent, and straightforward method of generating samples for TEM analysis. While this technique has been optimized for near-surface defects, it can be used with any application requiring plan view TEM analysis.

Fast Turn-around Failure Analysis of Metal Interconnection Using FIB and LA ICP-MS

2010 ◽  
Author(s):  
Zixiao Pan ◽  
Wei Wei ◽  
Fuhe Li
Keyword(s):  
Failure Analysis ◽  
Inductively Coupled Plasma ◽  
Structural Damage ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Detection Sensitivity ◽  
Chemical Contamination ◽  
Inductively Coupled ◽  
Minimal Sample ◽  
Icp Ms

Abstract This paper introduces our effort in failure analysis of a 200 nm thick metal interconnection on a glass substrate and covered with a passivation layer. Structural damage in localized areas of the metal interconnections was observed with the aid of focused ion beam (FIB) cross-sectioning. Laser ablation inductively coupled plasma mass spectroscopy (LA ICP-MS) was then applied to the problematic areas on the interconnection for chemical survey. LA ICP-MS showed direct evidence of localized chemical contamination, which has likely led to corrosion (or over-etching) of the metal interconnection and the assembly failure. Due to the high detection sensitivity of LA ICP-MS and its compatibility with insulating material analysis, minimal sample preparation is required. As a result, the combination of FIB and LA ICP-MS enabled successful meso-scale failure analysis with fast turnaround and reasonable cost.

Application of FIB Circuit Edit in Analysis of Memory Failure of SOI Devices

2006 ◽  
Author(s):  
Z. G. Song ◽  
S. K. Loh ◽  
X. H. Zheng ◽  
S.P. Neo ◽  
C. K. Oh
Keyword(s):  
Focused Ion Beam ◽  
Ion Beam ◽  
Electrical Characterization ◽  
Silicon On Insulator ◽  
First Case ◽  
Edx Analyses ◽  
Memory Failure ◽  
Soi Devices ◽  
Voltage Contrast ◽  
Soi Technology

Abstract This article presents two cases to demonstrate the application of focused ion beam (FIB) circuit edit in analysis of memory failure of silicon on insulator (SOI) devices using XTEM and EDX analyses. The first case was a single bit failure of SRAM units manufactured with 90 nm technology in SOI wafer. The second case was the whole column failure with a single bit pass for a SRAM unit. From the results, it was concluded that FIB circuit edit and electrical characterization is a good methodology for further narrowing down the defective location of memory failure, especially for SOI technology, where contact-level passive voltage contrast is not suitable.

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