Stress Reduction during Silicon Thinning Using Thermal Relaxation and 3D Curvature Correction Techniques

Author(s):  
Jim Colvin ◽  
Heenal Patel ◽  
Timothy Hazeldine

Abstract Backside sample preparation is required by many post silicon validation techniques like FIB (Focused Ion Beam) circuit editing and optical probing using Photon Emission or Laser Stimulus methods [1]. In spite of many conventional methods of silicon thinning and polishing, some challenges remain as new packages are introduced. With large die packages the issue of cracking during backside thinning is arising due to package curvature stress. 3D profile methods will be shown in conjunction with thermal relaxation to alleviate silicon center to edge variance allowing sample prep of large areas with thicknesses below 10μm. Thinning and polishing methods will be shown to be interactive with the device heated; demonstrating both thermal stress reduction coupled with curvature reduction.

2021 ◽  
Author(s):  
Tony Colpaert ◽  
Stefaan Verleye

Abstract This paper describes a fast and effective sample preparation method to allow backside fault localization on GaN package devices. Backside analysis by Photon Emission Microscopy (PEM) is becoming preferable to frontside analysis when the die is covered by metal layers. This paper describes an optimized method for backside sample preparation on GaN package devices having a thick heavily doped p-type silicon substrate. The method combines mechanical and chemical deprocessing steps, resulting in a fast and effective sample preparation technique for PEM analysis. Additionally, the laser marking process parameters to facilitate orientation during the final physical failure analysis by Focused Ion Beam (FIB) are also shared.


Author(s):  
John F. Walker ◽  
James K. Odum ◽  
Peter D. Carleson

With the realisation that the critical dimensions in integrated circuits are shrinking to the point where scanning electron microscopy (SEM) techniques are not sufficiently accurate for many applications, advanced semiconductor fabs are looking to the increased resolution and analytical functionality of transmission electron microscopy (TEM) in failure and process analysis. TEM sample preparation is traditionally labour-intensive and needs skilled technical support but, with the acceptance of focused ion beam (FIB) workstations, this preparation and subsequent analysis is now becoming more routine. The reasons are: more reliable preparation with less risk of catastrophic breaking on unique specimens, highly site-specific preparation capable of viewing individual, sub-100 nm features, thin and uniform membranes even with tungsten plugs, and fast and easy preparation techniques.The initial stages of sample preparation involves preparing a sub-100 um sliver mounted on a TEM grid. When mounting this sliver on the grid, care must be taken to prevent any strain from being transferred to the silicon.


2002 ◽  
Vol 733 ◽  
Author(s):  
Brock McCabe ◽  
Steven Nutt ◽  
Brent Viers ◽  
Tim Haddad

AbstractPolyhedral Oligomeric Silsequioxane molecules have been incorporated into a commercial polyurethane formulation to produce nanocomposite polyurethane foam. This tiny POSS silica molecule has been used successfully to enhance the performance of polymer systems using co-polymerization and blend strategies. In our investigation, we chose a high-temperature MDI Polyurethane resin foam currently used in military development projects. For the nanofiller, or “blend”, Cp7T7(OH)3 POSS was chosen. Structural characterization was accomplished by TEM and SEM to determine POSS dispersion and cell morphology, respectively. Thermal behavior was investigated by TGA. Two methods of TEM sample preparation were employed, Focused Ion Beam and Ultramicrotomy (room temperature).


Author(s):  
Ching Shan Sung ◽  
Hsiu Ting Lee ◽  
Jian Shing Luo

Abstract Transmission electron microscopy (TEM) plays an important role in the structural analysis and characterization of materials for process evaluation and failure analysis in the integrated circuit (IC) industry as device shrinkage continues. It is well known that a high quality TEM sample is one of the keys which enables to facilitate successful TEM analysis. This paper demonstrates a few examples to show the tricks on positioning, protection deposition, sample dicing, and focused ion beam milling of the TEM sample preparation for advanced DRAMs. The micro-structures of the devices and samples architectures were observed by using cross sectional transmission electron microscopy, scanning electron microscopy, and optical microscopy. Following these tricks can help readers to prepare TEM samples with higher quality and efficiency.


Author(s):  
Jian-Shing Luo ◽  
Hsiu Ting Lee

Abstract Several methods are used to invert samples 180 deg in a dual beam focused ion beam (FIB) system for backside milling by a specific in-situ lift out system or stages. However, most of those methods occupied too much time on FIB systems or requires a specific in-situ lift out system. This paper provides a novel transmission electron microscopy (TEM) sample preparation method to eliminate the curtain effect completely by a combination of backside milling and sample dicing with low cost and less FIB time. The procedures of the TEM pre-thinned sample preparation method using a combination of sample dicing and backside milling are described step by step. From the analysis results, the method has applied successfully to eliminate the curtain effect of dual beam FIB TEM samples for both random and site specific addresses.


Author(s):  
Chin Kai Liu ◽  
Chi Jen. Chen ◽  
Jeh Yan.Chiou ◽  
David Su

Abstract Focused ion beam (FIB) has become a useful tool in the Integrated Circuit (IC) industry, It is playing an important role in Failure Analysis (FA), circuit repair and Transmission Electron Microscopy (TEM) specimen preparation. In particular, preparation of TEM samples using FIB has become popular within the last ten years [1]; the progress in this field is well documented. Given the usefulness of FIB, “Artifact” however is a very sensitive issue in TEM inspections. The ability to identify those artifacts in TEM analysis is an important as to understanding the significance of pictures In this paper, we will describe how to measure the damages introduced by FIB sample preparation and introduce a better way to prevent such kind of artifacts.


Author(s):  
Julien Goxe ◽  
Béatrice Vanhuffel ◽  
Marie Castignolles ◽  
Thomas Zirilli

Abstract Passive Voltage Contrast (PVC) in a Scanning Electron Microscope (SEM) or a Focused Ion Beam (FIB) is a key Failure Analysis (FA) technique to highlight a leaky gate. The introduction of Silicon On Insulator (SOI) substrate in our recent automotive analog mixed-signal technology highlighted a new challenge: the Bottom Oxide (BOX) layer, by isolating the Silicon Active Area from the bulk made PVC technique less effective in finding leaky MOSFET gates. A solution involving sample preparation performed with standard FA toolset is proposed to enhance PVC on SOI substrate.


Author(s):  
Roger Alvis ◽  
Jeff Blackwood ◽  
Sang-Hoon Lee ◽  
Matthew Bray

Abstract Semiconductor devices with critical dimensions less than 20nm are now being manufactured in volume. A challenge facing the failure analysis and process-monitoring community is two-fold. The first challenge of TEM sample prep of such small devices is that the basic need to end-point on a feature-of-interest pushes the imaging limit of the instrument being used to prepare the lamella. The second challenge posed by advanced devices is to prepare an artifact-free lamella from non-planar devices such as finFETs as well as from structures incorporating ‘non-traditional’ materials. These challenges are presently overcome in many advanced logic and memory devices in the focused ion beam-based TEM sample preparation processes by inverting the specimen prior to thinning to electron transparency. This paper reports a highthroughput method for the routine preparation of artifact-free TEM lamella of 20nm thickness, or less.


Author(s):  
Romaneh Jalilian ◽  
David Mudd ◽  
Neil Torrez ◽  
Jose Rivera ◽  
Mehdi M. Yazdanpanah ◽  
...  

Abstract The sample preparation for transmission electron microscope can be done using a method known as "lift-out". This paper demonstrates a method of using a silver-gallium nanoneedle array for a quicker sharpening process of tungsten probes with better sample viewing, covering the fabrication steps and performance of needle-tipped probes for lift-out process. First, an array of high aspect ratio silver-gallium nanoneedles was fabricated and coated to improve their conductivity and strength. Then, the nanoneedles were welded to a regular tungsten probe in the focused ion beam system at the desired angle, and used as a sharp probe for lift-out. The paper demonstrates the superior mechanical properties of crystalline silver-gallium metallic nanoneedles. Finally, a weldless lift-out process is described whereby a nano-fork gripper was fabricated by attaching two nanoneedles to a tungsten probe.


Author(s):  
P. Perdu ◽  
G. Perez ◽  
M. Dupire ◽  
B. Benteo

Abstract To debug ASIC we likely use accurate tools such as an electron beam tester (Ebeam tester) and a Focused Ion Beam (FIB). Interactions between ions or electrons and the target device build charge up on its upper glassivation layer. This charge up could trigger several problems. With Ebeam testing, it sharply decreases voltage contrast during Image Fault Analysis and hide static voltage contrast. During ASIC reconfiguration with FIB, it could induce damages in the glassivation layer. Sample preparation is getting a key issue and we show how we can deal with it by optimizing carbon coating of the devices. Coating is done by an evaporator. For focused ion beam reconfiguration, we need a very thick coating. Otherwise the coating could be sputtered away due to imaging. This coating is use either to avoid charge-up on glassivated devices or as a sacrificial layer to avoid short circuits on unglassivated devices. For electron beam Testing, we need a very thin coating, we are now using an electrical characterization method with an insitu control system to obtain the right thin thickness. Carbon coating is a very cheap and useful method for sample preparation. It needs to be tuned according to the tool used.


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