In-Line Defects Overlaying with Functional Failures and Characterization for Fast Defect Learning and Fast Yield Improvement

2014 ◽  
Author(s):  
Zhigang Song ◽  
Oliver D. Patterson ◽  
Qian Xu
Keyword(s):  
Failure Analysis ◽  
Technology Development ◽  
Semiconductor Device ◽  
Development Stage ◽  
Line Defect ◽  
Defect Inspection ◽  
Yield Improvement ◽  
Root Cause ◽  
Manufacturing Yield ◽  
The Impact

Abstract Process defects, either random or systematic, are often the top killers of any semiconductor device. Process defect learning and reduction are the main focuses in both technology development stage and product manufacturing yield ramp stage. In order to achieve fast defect learning, in-line defect inspection is implemented in critical layers during wafer manufacturing. In-line defect inspection is able to detect defects. However, in-line defect inspection alone cannot predict the impact of defects on device functional yield. Failure analysis is an effective method of finding the defects which really cause device functional failures. However, often, the defects found by failure analysis are very different from the original defects, making it difficult to understand the root cause. This paper will describe a methodology how to combine in-line defect inspection and failure analysis together to found the top killer defects and accelerate their root cause identification for fast defect learning and yield improvement.

Logic Yield Learning Vehicle Failure Analysis in Technology Development

2012 ◽  
Author(s):  
Zhigang Song ◽  
Felix Beaudoin ◽  
Stephen Lucarini ◽  
Stephen Wu ◽  
Yunyu Wang ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Technology Development ◽  
Development Stage ◽  
Logic Circuits ◽  
Product Logic ◽  
Microelectronic Technology ◽  
Yield Learning ◽  
Weak Points ◽  
Product Manufacturing ◽  
Manufacturing Yield

Abstract With the microelectronic technology progresses in nanometer realm, like SRAM, logic circuits and structures are also becoming dense and more sensitive to process variation. Logic failures may have different root causes from SRAM failure. If these technology weak points for logic circuits are not detected and resolved during the technology development stage, they will greatly affect the product manufacturing yield ramp, leading to longer time of design to market. In this paper, we present a logic yield learning methodology based on an inline logic vehicle, which includes several scan chains of different latch types representative of product logic. Failure analysis for the low yield wafers had revealed several killer defects associated with logic circuits. A few examples of the systematic failures unique to logic circuits will be presented. In combination with SRAM yield learning, logic yield learning makes the technology development more robust thus improving manufacturability.

In-Line Defect to Bitmap Signature Correlation: A Shortcut to Physical FA Results

2000 ◽  
Author(s):  
Julie Segal ◽  
Arman Sagatelian ◽  
Bob Hodgkins ◽  
Tom Ho ◽  
Ben Chu ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Integrated Circuit ◽  
Failure Mechanisms ◽  
Memory Devices ◽  
Line Defect ◽  
Yield Improvement ◽  
Electrical Test ◽  
Large Numbers ◽  
Improvement Process ◽  
Existing Data

Abstract Physical failure analysis (FA) of integrated circuit devices that fail electrical test is an important part of the yield improvement process. This article describes how the analysis of existing data from arrayed devices can be used to replace physical FA of some electrical test failures, and increase the value of physical FA results. The discussion is limited to pre-repair results. The key is to use classified bitmaps and determine which signature classification correlates to which type of in-line defect. Using this technique, physical failure mechanisms can be determined for large numbers of failures on a scale that would be unfeasible with de-processing and physical FA. If the bitmaps are classified, two-way correlation can be performed: in-line defect to bitmap failure, as well as bitmap signature to in-line defect. Results also demonstrate the value of analyzing memory devices failures, even those that can be repaired, to gain understanding of defect mechanisms.

Leveraging Root Cause Deconvolution Analysis for Logic Yield Ramping

2013 ◽  
Author(s):  
Yan Pan ◽  
Atul Chittora ◽  
Kannan Sekar ◽  
Goh Szu Huat ◽  
You Guo Feng ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Comprehensive Analysis ◽  
Paper Briefly ◽  
Yield Improvement ◽  
Deconvolution Analysis ◽  
Analysis Techniques ◽  
Root Cause ◽  
Conventional Analysis ◽  
Analysis System ◽  
Over Time

Abstract The root cause deconvolution (RCD) provides an easy-to-understand defect Pareto, together with targeted physical failure analysis candidates. Unfortunately, even the RCD analysis also has some assumptions and limitations, and its result cannot always be interpreted literally. This calls for a variety of conventional yield analysis techniques to be adopted in parallel to improve the confidence in the RCD results. This paper briefly introduces the RCD analysis and explains how it distinguishes itself from other conventional volume diagnosis analysis techniques. Its typical inputs and outputs are discussed as well. Next, the paper focuses on two case studies where the authors leverage RCD for logic yield improvement together with other conventional analysis techniques. It then proposes a comprehensive analysis system that is backed up by accumulating RCD results over time and across different design IPs.

Contextual Failure Analysis Improves Reliability While Pushing the Envelope of Extended Reach Wells in a Giant Brown Field, UAE

2021 ◽  
Author(s):  
Elena Cantarelli ◽  
Khoa Le Pham Dang ◽  
Hernan Melgares Escalera
Keyword(s):  
Quality Improvement ◽  
Service Quality ◽  
Failure Analysis ◽  
Failure Modes ◽  
Action Plan ◽  
Comparative Approach ◽  
Risk Matrix ◽  
Priority List ◽  
Root Cause ◽  
The Impact

Abstract The current combination of increasingly complex wellbores and tightening budgets forces operators to do more with less and find new ways to expand the drilling envelop. Often this pushes the parameters to the limit in order to achieve faster penetration rates. Operating at the limit or beyond impacts equipment reliability and project cost. A thorough failure analysis of the root cause(s) of every incident can help identify and address areas that need improvement. Identifying a cause fosters improvement while it simultaneously pushes the boundaries so the profitability of mature assets can be maximized. Typical failure analysis attempts to determine the cause of a failure and establish corrective actions to prevent reoccurrence. In a large extended reach drilling project targeting a mature field, the approach to a single failure was expanded and projected in a proactive manner to anticipate the impact of current failure modes in future more challenging scenarios. This innovative method combines the classic failure analysis approach with a comparative approach designed to identify and classify each factor that contributed to the failure. This information is then compiled into a dynamic predictive risk matrix to improve the planning. This method, thanks to the contextualization of individual failures and the multi-facet comparative analysis, revealed a pattern between reliability trends and environmental challenges. The pattern was correlated with the increased drilling difficulty over the lifetime of the project, and suggested that the long-established practices had to be revised to overcome the new scenario. The analysis contributed to the delineation of a strong action plan that immediately revealed a consistent service quality improvement quarter on quarter and nearly a 50% decrease in failure rate. The enhanced reliability had a direct impact on the performance that registered a significant reduction of the drilling time, thus lowering the overall well construction cost. In today's economics where cost reduction, resource optimization and sustainability are at the top of the operator's priority list, failure analysis has become paramount to ensure continuous improvement. Effective analytic methods to identify and eliminate showstoppers are needed to minimize unplanned events and deliver within budget. By digging deep into the root cause of incidents, this new approach to failure analysis enabled an enhanced, broader and more effective quality improvement plan that tackled service quality from multiple angles. From refining bottomhole assembly (BHA) design and risk matrix to drafting field guidelines and roadmaps, this approach also provided extra guidance and risk awareness for future well planning improvement. This particularly applies to mature fields where wellbore complexity increases at the same time budgets decrease and it's necessary to improve operational excellence to assure profitability.

Advanced Failure Analysis of Junction Profile Defect by Using EBAC/EBIC

2015 ◽  
Author(s):  
Jong Hak Lee ◽  
Jae Yoon Lee ◽  
Dae Woo Kim ◽  
Kyoung Wook Jung ◽  
Soo Yong Son
Keyword(s):  
Technology Development ◽  
Semiconductor Device ◽  
Image Sensor ◽  
Process Technology ◽  
Root Cause ◽  
Analysis Phase ◽  
Analysis Technique ◽  
In Cis ◽  
Atomic Probe ◽  
Circuit Density

Abstract As semiconductor device geometries shrink due to process technology development and circuit density rapidly increases, it is becoming extremely difficult to effectively analyze defects. Against this background, more precise and efficient techniques to analyze the root cause of defects is in constant demand. This paper proposes a method to quickly and accurately identify the true cause of device failure by using a nano probe EBAC/EBIC analysis technique. The most significant benefit of the EBAC/EBIC analysis technique is the ability to identify normal or abnormal circuit behavior with an intuitive image. This benefit can minimize the damage to a sample during the initial analysis phase, which has been an issue in the analysis of existing physical properties of semiconductors. In this paper, we identified the root cause of a series transistor defect in CIS (CMOS Image Sensor) product by using EBAC/EBIC (analysis) technique, and verified this with the assistance of SSRM (Scanning Spreading Resistance Microscopy) and APT (Atomic Probe Tomography). By doing so, we confirmed that the analysis technique proposed in this paper is very effective in identifying and pinpointing the true cause and location of the defect.

Embedded SRAM Bitmapping and Failure Analysis for Manufacturing Yield Improvement

2000 ◽  
Author(s):  
Jean-Yves Glacet ◽  
Fourmun Lee
Keyword(s):  
Failure Analysis ◽  
Failure Modes ◽  
Monitoring Tool ◽  
Yield Improvement ◽  
Electrical Failure ◽  
Failure Data ◽  
Manufacturing Line ◽  
Significant Yield ◽  
Manufacturing Yield ◽  
Embedded Sram

Abstract SRAM bitmapping and failure analysis have been used as a driver for continuous yield improvement during pre-qualification manufacturing of a microcontroller. The combination of the embedded SRAM electrical failure data and failure analysis results was used to generate a pareto of failure modes and failure mechanisms and establish a correlation between the two. Bitmap trend charts can be used as a manufacturing line monitoring tool to supplement traditional in-line inspection. Identification of manufacturing issues can be obtained from bit failure information and compared with in-line inspection results to quickly identify which specific process module is responsible for a significant yield loss.

Fast Root Cause Identification Using Combination of Failure Analysis and In-Line Inspection

2017 ◽  
Author(s):  
Zhigang Song ◽  
Weihao Weng ◽  
Brett Engel
Keyword(s):  
Failure Analysis ◽  
Process Development ◽  
Second Step ◽  
Line Defect ◽  
Semiconductor Technology ◽  
Process Step ◽  
Root Cause ◽  
The Past ◽  
Root Cause Identification ◽  
The Relationship

Abstract Failure analysis plays an important role in yield improvement during semiconductor process development and device manufacturing. It includes two main steps. The first step is to find the defect and the second step is to identify the root cause. In the past, failure analysis mainly focused on the first step, namely how to find the defect for a failure; because in the previous generations of technology, once the defect was found, its root cause was relatively easy to be understood. As the current advanced semiconductor technology has become tremendously complicated, especially 3D devices, like FinFET, a defect found by failure analysis can be substantially transformed from its original defect by subsequent processes and can be totally different from its origin in size and shape. Thus, sometimes, the second step, identifying the root cause for a defect becomes more challenging and takes more time than the first step. With combination of failure analysis and inline inspection, it enables us to establish the relationship between the failure analysis defect and an in-line defect. This can link the defect for a device functional failure to its source layer and process step more quickly, leading to fast root cause identification. In this paper, the methodology was validated by fast identification of the root causes for three case studies in the latest FinFET technology.

A New Failure Analysis Flow of Gate Oxide Integrity Failure in Wafer Fabrication

2009 ◽  
Author(s):  
Hua Younan ◽  
Chu Susan ◽  
Gui Dong ◽  
Mo Zhiqiang ◽  
Xing Zhenxiang ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Gate Dielectric ◽  
Dielectric Breakdown ◽  
Defect Density ◽  
Gate Oxide ◽  
Oxide Thickness ◽  
Fault Isolation ◽  
Wafer Fabrication ◽  
Root Cause ◽  
Gate Oxide Integrity

Abstract As device feature size continues to shrink, the reducing gate oxide thickness puts more stringent requirements on gate dielectric quality in terms of defect density and contamination concentration. As a result, analyzing gate oxide integrity and dielectric breakdown failures during wafer fabrication becomes more difficult. Using a traditional FA flow and methods some defects were observed after electrical fault isolation using emission microscopic tools such as EMMI and TIVA. Even with some success with conventional FA the root cause was unclear. In this paper, we will propose an analysis flow for GOI failures to improve FA’s success rate. In this new proposed flow both a chemical method, Wright Etch, and SIMS analysis techniques are employed to identify root cause of the GOI failures after EFA fault isolation. In general, the shape of the defect might provide information as to the root cause of the GOI failure, whether related to PID or contamination. However, Wright Etch results are inadequate to answer the questions of whether the failure is caused by contamination or not. If there is a contaminate another technique is required to determine what the contaminant is and where it comes from. If the failure is confirmed to be due to contamination, SIMS is used to further determine the contamination source at the ppm-ppb level. In this paper, a real case of GOI failure will be discussed and presented. Using the new failure analysis flow, the root cause was identified to be iron contamination introduced from a worn out part made of stainless steel.

Burn-in Failure Analysis of 0.5μm 1MB SRAM: Barrier Glue Layer Cracks and Tungsten Plug “Worm Holes”

1996 ◽  
Author(s):  
E. Widener ◽  
S. Tatti ◽  
P. Schani ◽  
S. Crown ◽  
B. Dunnigan ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Product Quality ◽  
Cmos Process ◽  
Designed Experiments ◽  
Root Cause ◽  
Poly Silicon ◽  
New Process ◽  
Supply Current ◽  
Electrical Analysis ◽  
Current Characteristics

Abstract A new 0.5 um 1 Megabit SRAM which employed a double metal, triple poly CMOS process with Tungsten plug metal to poly /silicon contacts was introduced. During burn-in of this product, high currents, apparently due to electrical overstress, were experienced. Electrical analysis showed abnormal supply current characteristics at high voltages. Failure analysis identified the sites of the high currents of the bum-in rejects and discovered cracks in the glue layer prior to Tungsten deposition as the root cause of the failure. The glue layer cracks allowed a reaction with the poly/silicon, causing opens at the bottom of contacts. These floating nodes caused high currents and often latch-up during burn-in. Designed experiments in the wafer fab identified an improved glue layer process, which has been implemented. The new process shows improvement in burn in performance as well as outgoing product quality.

Analysis Approach on DMOS Transistor Vth Mismatch Due to Trapped Charges

2015 ◽  
Author(s):  
Hashim Ismail ◽  
Ang Chung Keow ◽  
Kenny Gan Chye Siong
Keyword(s):  
Failure Analysis ◽  
Threshold Voltage ◽  
Gate Oxide ◽  
Analysis Approach ◽  
Test Results ◽  
Root Cause ◽  
Switching Event ◽  
Output Transistor ◽  
Event Based ◽  
Trapped Charge

Abstract An output switching malfunction was reported on a bridge driver IC. The electrical verification testing revealed evidence of an earlier over current condition resulting from an abnormal voltage sense during a switching event. Based on these test results, we developed the hypothesis that a threshold voltage mismatch existed between the sense transistor and the output transistor. This paper describes the failure analysis approach we used to characterize the threshold voltage mismatch as well as our approach to determine the root cause, which was trapped charge on the gate oxide of the sense transistor.

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