Fast Root Cause Identification Using Combination of Failure Analysis and In-Line Inspection

2017 ◽  
Author(s):  
Zhigang Song ◽  
Weihao Weng ◽  
Brett Engel
Keyword(s):  
Failure Analysis ◽  
Process Development ◽  
Second Step ◽  
Line Defect ◽  
Semiconductor Technology ◽  
Process Step ◽  
Root Cause ◽  
The Past ◽  
Root Cause Identification ◽  
The Relationship

Abstract Failure analysis plays an important role in yield improvement during semiconductor process development and device manufacturing. It includes two main steps. The first step is to find the defect and the second step is to identify the root cause. In the past, failure analysis mainly focused on the first step, namely how to find the defect for a failure; because in the previous generations of technology, once the defect was found, its root cause was relatively easy to be understood. As the current advanced semiconductor technology has become tremendously complicated, especially 3D devices, like FinFET, a defect found by failure analysis can be substantially transformed from its original defect by subsequent processes and can be totally different from its origin in size and shape. Thus, sometimes, the second step, identifying the root cause for a defect becomes more challenging and takes more time than the first step. With combination of failure analysis and inline inspection, it enables us to establish the relationship between the failure analysis defect and an in-line defect. This can link the defect for a device functional failure to its source layer and process step more quickly, leading to fast root cause identification. In this paper, the methodology was validated by fast identification of the root causes for three case studies in the latest FinFET technology.

Root Cause Analysis for Pin Leakage

2016 ◽  
Author(s):  
Zhigang Song ◽  
Jochonia Nxumalo ◽  
Manuel Villalobos ◽  
Sweta Pendyala
Keyword(s):  
Failure Analysis ◽  
Root Cause Analysis ◽  
Advanced Technology ◽  
Process Step ◽  
Cause Analysis ◽  
Hard Mask ◽  
Technology Node ◽  
Root Cause ◽  
Tools And Techniques

Abstract Pin leakage continues to be on the list of top yield detractors for microelectronics devices. It is simply manifested as elevated current with one pin or several pins during pin continuity test. Although many techniques are capable to globally localize the fault of pin leakage, root cause analysis and identification for it are still very challenging with today’s advanced failure analysis tools and techniques. It is because pin leakage can be caused by any type of defect, at any layer in the device and at any process step. This paper presents a case study to demonstrate how to combine multiple techniques to accurately identify the root cause of a pin leakage issue for a device manufactured using advanced technology node. The root cause was identified as under-etch issue during P+ implantation hard mask opening for ESD protection diode, causing P+ implantation missing, which was responsible for the nearly ohmic type pin leakage.

Advancement in Data Engineering and Feature Processing Workflow by Using Deep Learning Techniques for the Automation of ESP Failure Root Cause Analyses

2021 ◽  
Author(s):  
Saniya Karnik ◽  
Navya Yenuganti ◽  
Bonang Firmansyah Jusri ◽  
Supriya Gupta ◽  
Prasanna Nirgudkar ◽  
...  
Keyword(s):  
Deep Learning ◽  
Failure Analysis ◽  
Language Processing ◽  
Turnaround Time ◽  
Process Efficiency ◽  
Root Cause ◽  
Feature Processing ◽  
Learning Techniques ◽  
Electrical Submersible Pump ◽  
Root Cause Identification

Abstract Today, Electrical Submersible Pump (ESP) failure analysis is a tedious, human-intensive, and time-consuming activity involving dismantle, inspection, and failure analysis (DIFA) for each failure. This paper presents a novel artificial intelligence workflow using an ensemble of machine learning (ML) algorithms coupled with natural language processing (NLP) and deep learning (DL). The algorithms outlined in this paper bring together structured and unstructured data across equipment, production, operations, and failure reports to automate root cause identification and analysis post breakdown. This process will result in reduced turnaround time (TAT) and human effort thus drastically improving process efficiency.

scholarly journals “L’énigme du passé”. Vers les fondements du rapport entre l’histoire et la psychanalyse

2020 ◽  
Vol 10 (2) ◽  
pp. 70-87
Author(s):  
Paul Marinescu
Keyword(s):  
Second Step ◽  
Disciplinary Practices ◽  
Fundamental Structure ◽  
The Past ◽  
Psychoanalytic Concept ◽  
The Relationship ◽  
Guiding Questions

This article aims to address, by means of a two-step analysis, the foundations of the relationship between history and psychoanalysis as “disciplinary practices” that deal with the past. In the first step, I examine the different relationships between history and psychoanalysis but also the uses of psychoanalysis in historical approaches. My goal here is to situate the context and the guiding questions. As a second step, I try to show that Ricœur puts forward, in his book Memory, History, Forgetting, a major thesis regarding the foundations of the relationship between psychoanalysis and the hermeneutics of history. By means of the phenomenology of wounded memory, he identifies a fundamental structure of collective existence that provides the basis of this relationship. Finally, I seek to determine the scope of this structure, which takes the form of an originary trauma affecting the collective existence, by drawing an analogy with the psychoanalytic concept of afterwardsness.

Invisible Defect Root Cause Identification with Electrical and Chemical Analyses

2015 ◽  
Author(s):  
Zhigang Song ◽  
Yunyu Wang ◽  
Sweta Pendyala
Keyword(s):  
Advanced Technology ◽  
Semiconductor Technology ◽  
Root Cause ◽  
Transmission Electron ◽  
Increasing Trend ◽  
Transmission Electron Microscope Analysis ◽  
Electron Microscope Analysis ◽  
Scaling Down ◽  
Root Cause Identification ◽  
Technology Nodes

Abstract As semiconductor technology keeps scaling down, the conventional physical failure analysis processes have faced increasing challenges and encountered low success rate. It is not only because the defect causing a failure becomes tinier and tinier, but also because some of these defects themselves are invisible. Electrical nano-probing with narrowing down a defect to a single transistor has greatly increased the likeliness of finding a tiny defect in subsequent TEM (transmission Electron Microscope) analysis. However, there is still an increasing trend of encountering an invisible defect at most advanced technology nodes. This paper will present how to identify the root causes of three such invisible defects with the combination of electrical nano-probing and TEM chemical analysis.

Process Flow Employed for Parametric Test Structure Shorts Fault Isolation in 20 nm and Sub-20 nm Technologies in High Throughput Foundries

2017 ◽  
Author(s):  
Satish Kodali ◽  
Mia Nasimullah ◽  
Yuting Wei ◽  
Chong Khiam Oh ◽  
Felix Beaudoin
Keyword(s):  
Process Development ◽  
Fault Isolation ◽  
Predominant Role ◽  
Process Flow ◽  
Parametric Test ◽  
Root Cause ◽  
Development Cycle ◽  
Root Cause Identification ◽  
20 Nm ◽  
Low K

Abstract With increasing complexity involved in advance node semiconductor process development, dependability on parametric test structures has also increased significantly. Test structures play a predominant role throughout the entire development cycle of a product. It becomes very important to understand the root cause of failures at fastest pace to take necessary corrective actions. The use of ultra low K dielectrics for back end of line wafer build for advanced nodes created significant constraints on conventional beam imaging methods for fault isolation. This paper provides a streamlined process flow for root cause identification on shorts on advanced 20 nm and sub-20 nm technologies. Three unique cases are presented to demonstrate three typical situations identified in the process flow. They are blown capacitors, gate leakage, and resistance ladder short isolation.

Root Cause Finding of a Diode Leakage Failure Using Scanning Magnetic Microscopy and ToF-SIMS as Key Methods

2006 ◽  
Author(s):  
H. Preu ◽  
W. Mack ◽  
T. Kilger ◽  
B. Seidl ◽  
J. Walter ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Quantum Interference ◽  
Leakage Currents ◽  
Root Cause ◽  
Microelectronic Devices ◽  
Successful Approach ◽  
Magnetic Microscopy ◽  
Leakage Failure ◽  
Root Cause Identification

Abstract One challenge in failure analysis of microelectronic devices is the localization and root cause finding of leakage currents in passives. In this case study we present a successful approach for failure analysis of a diode leakage failure. An analytical flow will be introduced, which contains standard techniques as well as SQUID (superconducting quantum interference device) scanning magnetic microscopy and ToFSIMS as key methods for localization and root cause identification. [1]

Failure Mechanism Studies and Root Cause Identification of Nonstick on Pad on Microchip Al Bondpads

2014 ◽  
Author(s):  
Hua Younan ◽  
Zhou Yongkai ◽  
Chen Yixin ◽  
Fu Chao ◽  
Li Xiaomin
Keyword(s):  
Failure Analysis ◽  
Failure Mechanism ◽  
Wafer Fabrication ◽  
Assembly Process ◽  
Root Cause ◽  
Barrier Metal ◽  
Root Cause Identification ◽  
Induced Defects

Abstract It is well-known that underetch material, contamination, particle, pinholes and corrosion-induced defects on microchip Al bondpads will cause non-stick on pads (NSOP) issues. In this paper, the authors will further study NSOP problem and introduce one more NSOP failure mechanism due to Cu diffusion caused by poor Ta barrier metal. Based on our failure analysis results, the NSOP issue was not due to the assembly process, but due to the wafer fabrication. The failure mechanism might be that the barrier metal Ta was with pinholes, which caused Cu diffused out to the top Al layer, and then formed the “Bump-like” Cu defects and resulted in NSOP on Al bondpads during assembly process.

Advanced Scan Chain Failure Analysis Using Laser Modulation Mapping and Continuous Wave Probing

2011 ◽  
Author(s):  
Steven Kasapi ◽  
William Lo ◽  
Joy Liao ◽  
Bruce Cory ◽  
Howard Marks
Keyword(s):  
Failure Analysis ◽  
Continuous Wave ◽  
Wafer Level ◽  
Root Cause ◽  
Non Invasive ◽  
Laser Probing ◽  
Volume Yield ◽  
Scan Chain ◽  
Leakage Failure ◽  
Root Cause Identification

Abstract A variety of EFA techniques have been deployed to improve scan chain failure isolation. In contrast to other laser techniques, modulation mapping (MM) does not require electrically perturbing of the device. Beginning with a review of MM and continuous-wave (CW) probing as well as shift debug using MM, this paper presents three case studies involving scan chains with subtle resistive and leakage failure mechanisms, including transition, bridge, and slow-to-rise/fall failures, using a combination of these techniques. Combining modulation mapping with laser probing has proven to be a very effective and efficient methodology for isolating shift defects, even challenging timing-related shift defects. So far, every device submitted for physical failure analysis using this workflow has led to successful root cause identification. The techniques are sufficiently non-invasive and straightforward that they can be successfully applied at wafer level for volume, yield-oriented EFA.

Process Flow Employed for Parametric Test Structure Chain Opens Fault Isolation in 20 nm and Sub-20 nm Technologies in High Throughput Foundries

2016 ◽  
Author(s):  
Satish Kodali ◽  
Yinzhe Ma ◽  
Chong Khiam Oh ◽  
Wayne Zhao ◽  
Felix Beaudoin
Keyword(s):  
Cross Sections ◽  
Process Development ◽  
Fault Isolation ◽  
Flow Sheet ◽  
Process Flow ◽  
Parametric Test ◽  
Root Cause ◽  
Voltage Contrast ◽  
Root Cause Identification ◽  
20 Nm

Abstract With increasing complexity involved in advance node semiconductor process development, dependability on parametric test structures has also increased significantly. Test structures play a predominant role throughout the entire development cycle of a product. They are used to understand the process windows and also help to monitor the health of a line. This work provides a process flow sheet for root cause identification on chain opens on advanced 20 nm and sub-20 nm technologies setting a standard guideline for a specific category fail type. It provides a consistent way of attack in a much more streamlined fashion. Further, dependability on TEM rather than convention FIB cross-sections provides shortest time to root cause identification. Three typical cases encountered are discussed to demonstrate the idea: embedded chain opens by electron beam absorbed current (EBAC) isolation, chains opens at level by EBAC isolation, and chains opens at level by passive voltage contrast isolation.

Silicon Dislocation Enhanced by Dynamic Voltage Stress

2007 ◽  
Author(s):  
Yu-Cheng Lin ◽  
Rock Chen ◽  
Sanan Liang ◽  
Scott Liao ◽  
Chorng Niou ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Silicon Substrate ◽  
Reliability Test ◽  
Final Test ◽  
Functional Failure ◽  
Root Cause ◽  
Voltage Stress ◽  
Dynamic Voltage ◽  
Lightly Doped Drain ◽  
The Relationship

Abstract In reliability test some chips suffered functional failure. Through a series of failure analysis experiments, the root cause was determined to be a silicon dislocation across LDD (Lightly Doped Drain) area causing p-n junction leakage. However, those failed samples all passed both CP (Chip Probe) and FT (Final Test) monitor. Therefore, it is reasonable to suspect that DVS (dynamic voltage stress) may enhance minor dislocations already existing before CP and FT. To prove this hypothesis, an experiment was designed to find the relationship between DVS and the depth of dislocation in silicon substrate. In conclusion, DVS could enhance dislocation across LDD area, which may induce reliability failure. Moreover, reliability concerns on this finding will be discussed in this paper.

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