Logic Yield Learning Vehicle Failure Analysis in Technology Development

2012 ◽  
Author(s):  
Zhigang Song ◽  
Felix Beaudoin ◽  
Stephen Lucarini ◽  
Stephen Wu ◽  
Yunyu Wang ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Technology Development ◽  
Development Stage ◽  
Logic Circuits ◽  
Product Logic ◽  
Microelectronic Technology ◽  
Yield Learning ◽  
Weak Points ◽  
Product Manufacturing ◽  
Manufacturing Yield

Abstract With the microelectronic technology progresses in nanometer realm, like SRAM, logic circuits and structures are also becoming dense and more sensitive to process variation. Logic failures may have different root causes from SRAM failure. If these technology weak points for logic circuits are not detected and resolved during the technology development stage, they will greatly affect the product manufacturing yield ramp, leading to longer time of design to market. In this paper, we present a logic yield learning methodology based on an inline logic vehicle, which includes several scan chains of different latch types representative of product logic. Failure analysis for the low yield wafers had revealed several killer defects associated with logic circuits. A few examples of the systematic failures unique to logic circuits will be presented. In combination with SRAM yield learning, logic yield learning makes the technology development more robust thus improving manufacturability.

In-Line Defects Overlaying with Functional Failures and Characterization for Fast Defect Learning and Fast Yield Improvement

2014 ◽  
Author(s):  
Zhigang Song ◽  
Oliver D. Patterson ◽  
Qian Xu
Keyword(s):  
Failure Analysis ◽  
Technology Development ◽  
Semiconductor Device ◽  
Development Stage ◽  
Line Defect ◽  
Defect Inspection ◽  
Yield Improvement ◽  
Root Cause ◽  
Manufacturing Yield ◽  
The Impact

Abstract Process defects, either random or systematic, are often the top killers of any semiconductor device. Process defect learning and reduction are the main focuses in both technology development stage and product manufacturing yield ramp stage. In order to achieve fast defect learning, in-line defect inspection is implemented in critical layers during wafer manufacturing. In-line defect inspection is able to detect defects. However, in-line defect inspection alone cannot predict the impact of defects on device functional yield. Failure analysis is an effective method of finding the defects which really cause device functional failures. However, often, the defects found by failure analysis are very different from the original defects, making it difficult to understand the root cause. This paper will describe a methodology how to combine in-line defect inspection and failure analysis together to found the top killer defects and accelerate their root cause identification for fast defect learning and yield improvement.

Sub-20nm Device Voltage-Sensitive SRAM Characterization and Failure Analysis

2018 ◽  
Author(s):  
Seng Nguon Ting ◽  
Hsien-Ching Lo ◽  
Donald Nedeau ◽  
Aaron Sinnott ◽  
Felix Beaudoin
Keyword(s):  
Failure Analysis ◽  
High Performance ◽  
Yield Loss ◽  
Technology Development ◽  
High Density ◽  
High K ◽  
Yield Learning ◽  
Oxide Deposition ◽  
Edge Profile ◽  
High K Dielectric

Abstract With rapid scaling of semiconductor devices, new and more complicated challenges emerge as technology development progresses. In SRAM yield learning vehicles, it is becoming increasingly difficult to differentiate the voltage-sensitive SRAM yield loss from the expected hard bit-cells failures. It can only be accomplished by extensively leveraging yield, layout analysis and fault localization in sub-micron devices. In this paper, we describe the successful debugging of the yield gap observed between the High Density and the High Performance bit-cells. The SRAM yield loss is observed to be strongly modulated by different active sizing between two pull up (PU) bit-cells. Failure analysis focused at the weak point vicinity successfully identified abnormal poly edge profile with systematic High k Dielectric shorts. Tight active space on High Density cells led to limitation of complete trench gap-fill creating void filled with gate material. Thanks to this knowledge, the process was optimized with “Skip Active Atomic Level Oxide Deposition” step improving trench gap-fill margin.

Case Studies in Atomic Force Probe Analysis

2006 ◽  
Author(s):  
Randal Mulder ◽  
Sam Subramanian ◽  
Tony Chrastecky
Keyword(s):  
Failure Analysis ◽  
Case Studies ◽  
Light Emission ◽  
Electrical Characterization ◽  
Logic Circuits ◽  
Contrast Imaging ◽  
Atomic Force ◽  
Measuring Surface ◽  
Analysis Environment

Abstract The use of atomic force probe (AFP) analysis in the analysis of semiconductor devices is expanding from its initial purpose of solely characterizing CMOS transistors at the contact level with a parametric analyzer. Other uses found for the AFP include the full electrical characterization of failing SRAM bit cells, current contrast imaging of SOI transistors, measuring surface roughness, the probing of metallization layers to measure leakages, and use with other tools, such as light emission, to quickly localize and identify defects in logic circuits. This paper presents several case studies in regards to these activities and their results. These case studies demonstrate the versatility of the AFP. The needs and demands of the failure analysis environment have quickly expanded its use. These expanded capabilities make the AFP more valuable for the failure analysis community.

Advanced Scan Diagnosis Based Fault Isolation and Defect Identification for Yield Learning

2005 ◽  
Author(s):  
Chris Eddleman ◽  
Nagesh Tamarapalli ◽  
Wu-Tung Cheng
Keyword(s):  
Failure Analysis ◽  
Fault Location ◽  
Effective Means ◽  
Fault Isolation ◽  
Yield Enhancement ◽  
Yield Analysis ◽  
Isolation Techniques ◽  
Yield Learning ◽  
Time Required ◽  
Inspection Data

Abstract Yield analysis of sub-micron devices is an ever-increasing challenge. The difficulty is compounded by the lack of in-line inspection data as many companies adopt foundry or fab-less models for acquiring wafers. In this scenario, failure analysis is increasingly critical to help drive yields. Failure analysis is a process of fault isolation, or a method of isolating failures as precisely as possible followed by identification of a physical defect. As the number of transistors and metal layers increase, traditional fault isolation techniques are less successful at isolating a cause of failures. Costs are increasing due to the amount of time needed to locate the physical defect. One solution to the yield analysis problem is scan diagnosis based fault isolation. Previous scan diagnosis based techniques were limited with little information about the type of fault and confidence of diagnosis. With new scan diagnosis algorithms it is now possible to not only isolate, but to identify the type of fault as well as assigning a confidence ranking prior to any destructive analysis. This paper presents multiple case studies illustrating the application of scan diagnosis as an effective means to achieve yield enhancement. The advanced scan diagnostic tool used in this study provides information about the fault type as well as fault location. This information focuses failure analysis efforts toward a suspected defect, decreasing the cycle time required to determine root cause, as well as increasing the over all success rate.

Analysis of Development Trends in Low Energy Advanced Convergence Building Technology

2017 ◽  
Vol 872 ◽  
pp. 125-129
Author(s):  
Young Duk Koo ◽  
Dae Hyun Jeong
Keyword(s):  
Technology Development ◽  
Development Stage ◽  
Low Energy ◽  
Maturity Stage ◽  
Joint Research ◽  
Building Technology ◽  
The Usa ◽  
Technology Convergence ◽  
Map Analysis ◽  
Technology Level

The purpose of this study is to conduct a technology-level analysis and draw implications regarding the development of low energy advanced convergence building technology by utilizing information in research papers. With this aim, a citation analysis, a technology development stage analysis, a network analysis, and a technology associative map analysis were undertaken. The results showed that countries including the USA and China have carried out much research in the development of low energy advanced convergence building technology, and the technology level was found to have reached the maturity stage. Also, joint research has been conducted by region, and technology development has been done actively through ICT technology convergence such as electric and electronics and information communication. These analyzed results are expected to furnish useful information for strategy building in the development of low energy advanced convergence building technology.

SRAM Bitcell Defect Identification Methodology Using Electrical Failure Analysis Data

2020 ◽  
Author(s):  
Hyungtae Kim ◽  
Geonho Kim ◽  
Yunrong Li ◽  
Jinyong Jeong ◽  
Youngdae Kim
Keyword(s):  
Failure Analysis ◽  
Technology Development ◽  
New Technology ◽  
Random Access ◽  
Analysis Data ◽  
Test Method ◽  
Design For Test ◽  
Defect Identification ◽  
Electrical Failure ◽  
Efficient Test

Abstract Static Random Access Memory (SRAM) has long been used for a new technology development vehicle because it is sensitive to process defects due to its high density and minimum feature size. In addition, failure location can be accurately predicted because of the highly structured architecture. Thus, fast and accurate Failure Analysis (FA) of the SRAM failure is crucial for the success of new technology learning and development. It is often quite time consuming to identify defects through conventional physical failure analysis techniques. In this paper, we present an advanced defect identification methodology for SRAM bitcell failures with fast speed and high accuracy based on the bitcell transistor analog characteristics from special design for test (DFT) features, Direct Bitcell Access (DBA). This technique has the advantage to shorten FA throughput time due to a time efficient test method and an intuitive failure analysis method based on Electrical Failure Analysis (EFA) without destructive analysis. In addition, all the defects in a wafer can be analyzed and improved simultaneously utilizing the proposed defect identification methodology. Some successful case studies are also discussed to demonstrate the efficiency of the proposed defect identification methodology.

Applications of 3D X-Ray Microscopy for Advanced Package Development

2011 ◽  
Vol 2011 (1) ◽  
pp. 001078-001083 ◽  
Author(s):  
K. Fahey ◽  
R. Estrada ◽  
L. Mirkarimi ◽  
R. Katkar ◽  
D. Buckminster ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Flip Chip ◽  
Development Stage ◽  
Development Effort ◽  
X Ray ◽  
Structural Details ◽  
Volumetric Images ◽  
Advanced Packaging ◽  
Solder Fatigue ◽  
Non Destructive

This paper describes the utilization of non-destructive imaging using 3D x-ray microscopy for package development and failure analysis. Four case studies are discussed to explain our methodology and its impact on our advanced packaging development effort. Identifying and locating failures embedded deep inside the package, such as a solder fatigue failure within a flip chip package, without the need for physical cross-sectioning is of substantial benefit because it preserves the package for further analysis. Also of utility is the ability to reveal the structural details of the package while producing superior quality 2D and volumetric images. The technique could be used not only for analysis of defects and failures, but also to characterize geometries and morphologies during the process and package development stage.

scholarly journals A Cost-Effective and Transferable Methodology for Rooftop PV Potential Assessment in Developing Countries

Energies ◽  
2020 ◽  
Vol 13 (10) ◽  
pp. 2501 ◽  
Author(s):  
Phuong Minh Khuong ◽  
Russell McKenna ◽  
Wolf Fichtner
Keyword(s):  
Technology Development ◽  
Developing Economies ◽  
Cost Effective ◽  
Development Stage ◽  
Market Potential ◽  
The Self ◽  
Priority Order ◽  
Efficient Uptake ◽  
Framework Conditions ◽  
Module Efficiency

The efficient uptake of decentralized solar rooftop photovoltaics (PV) is in some cases hindered by ineffective energy and political framework conditions. These may be based on inaccurate and uncertain potential assessments in the early development stage of the solar market. This paper develops a more accurate, cost-effective, and robust potential assessment for emerging and developing economies. Adjusting the module efficiency corresponding to regional and household conditions improves the output accuracy. The rooftop PV market changes are simulated regarding different input changes and policy designs, including changing the Feed-In Tariff (FIT), grid tariff, and technology development. In the case study, the market potential in Vietnam is estimated at 260–280 TWh/a and is clustered into six groups in priority order, in which Hanoi and Ho Chi Minh need the most policy focus. Changing the FIT from 8.83 to 9 Euro cent/kWh and using different regional FITs can activate an additional 16% of the market and lead to a possible 28 million Euro benefit. Increasing the grid tariff to 8.7 cents/kWh could activate the self-consumption model, and the self-sufficient market can be guaranteed in the case of CAPEX and OPEX being lower than 650 Euro/kWp. Future developments of the method should focus on combining this top-down method with detailed bottom-up approaches.

Study on the Relationship Between Technology Complex Degree and Technology Transitional Speed Based on Patents Information—The Case of PDP Industry

2016 ◽  
Vol 13 (10) ◽  
pp. 7617-7622
Author(s):  
Xie Yuming ◽  
Shao Yunfei
Keyword(s):  
Negative Correlation ◽  
Transition Rate ◽  
Development Process ◽  
Technology Development ◽  
Development Stage ◽  
Patent Analysis ◽  
Technology Transition ◽  
Complex Technology ◽  
Technological Transition ◽  
The Relationship

This paper selects PDP industry technology development process as an analytical object, using means of patent analysis, to analyze the PDP industry,s technological track, the degree of technical complexity, technical transition rate to find a workable way of this industry for the management of complex technologies. Through research we found that the complexity of the technology and technology transition is in the existence of a negative correlation. The degree of technical complexity increased with the expansion of technology networks and the speed of technological transition has decreased. So for participation in R&D of complex technology businesses should focus on the development stage of a complex technology, and adjust technical R&D strategy timely.

Sign in / Sign up

Export Citation Format

Share Document