A Case Study—Improving FIB Passive Voltage Contrast Imaging for Deep N-Well Circuits

2015 ◽  
Author(s):  
Randal Mulder
Keyword(s):  
Failure Analysis ◽  
Failure Mechanism ◽  
Fault Location ◽  
Analog Circuit ◽  
Design Feature ◽  
Previous Attempt ◽  
Contrast Imaging ◽  
Circuit Blocks ◽  
Voltage Contrast

Abstract This paper presents a case study of a customer return that failed functional testing on the production tester. Investigation by applications and design engineering identified several analog circuit blocks where a possible failure mechanism could be located causing the functional failure mode seen at test. The identified circuit blocks all resided in deep n-well structures preventing traditional passive voltage contrast imaging (PVC) from being used to isolate the fault location. Neither functional probing nor active voltage contrast imaging were viable options to isolate the failure mechanism to a specific node. The analyst, having a good understanding of the principles of PVC and the difficulties associated with PVC imaging of deep n-well circuits, took advantage of a design feature in the device to restore the ability to perform passive voltage contrast imaging on these circuits. Using this enhanced PVC capability, two polysilicon capacitors with degraded oxide integrity were easily identified. This degraded oxide was verified to cause abnormal leakage to the substrate by means of nanoprobe analysis. Without identifying and taking advantage of a design feature not intended for failure analysis, locating these damage poly capacitors would have been extremely difficult because existing analysis techniques could only localize the failure to a number of circuit blocks. This paper presents a brief detailed over-view of PVC imaging, the issues with PVC imaging of deep n-well circuits, and an example of a previous attempt to overcome the deep n-well PVC problem. This review is then followed by the case study demonstrating the steps taken to restore PVC capability and concludes with recommendations for design for failure analysis (DFA).

Case Study in Fault Isolation of a Metal Short for Yield Enhancement

2010 ◽  
Author(s):  
Sarven Ipek ◽  
David Grosjean
Keyword(s):  
Failure Analysis ◽  
Failure Mechanism ◽  
Photon Emission ◽  
Fault Isolation ◽  
Yield Enhancement ◽  
Analysis Technique ◽  
Laser Signal ◽  
Signal Injection ◽  
Microscopy Techniques

Abstract The application of an individual failure analysis technique rarely provides the failure mechanism. More typically, the results of numerous techniques need to be combined and considered to locate and verify the correct failure mechanism. This paper describes a particular case in which different microscopy techniques (photon emission, laser signal injection, and current imaging) gave clues to the problem, which then needed to be combined with manual probing and a thorough understanding of the circuit to locate the defect. By combining probing of that circuit block with the mapping and emission results, the authors were able to understand the photon emission spots and the laser signal injection microscopy (LSIM) signatures to be effects of the defect. It also helped them narrow down the search for the defect so that LSIM on a small part of the circuit could lead to the actual defect.

Case Study Failure Analysis of an Ultra-High Vacuum Enclosure Made of a Silicon Chip and Borosilicate Glass for the Cold Atom Laboratory

2017 ◽  
Author(s):  
Gil Garteiz ◽  
Javeck Verdugo ◽  
David Aveline ◽  
Eric Williams ◽  
Arvid Croonquist ◽  
...  
Keyword(s):  
Sample Preparation ◽  
Failure Analysis ◽  
Failure Mechanism ◽  
Borosilicate Glass ◽  
High Vacuum ◽  
Cold Atom ◽  
Fault Isolation ◽  
Ultra High Vacuum ◽  
Liquid Bath

Abstract In this paper, a failure analysis case study on a custom-built vacuum enclosure is presented. The enclosure’s unique construction and project requirement to preserve the maximum number of units for potential future use in space necessitated a fluorocarbon liquid bath for fault isolation and meticulous sample preparation to preserve the failure mechanism during failure analysis.

The SRAM Soft Failure Analysis with SNM & TR Characterization by Nanoprobing in Sub 45nm

2009 ◽  
Author(s):  
Jakyung Hong ◽  
S.J. Cho ◽  
Y.W. Han ◽  
H.S. Choi ◽  
T.E. Kim ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Failure Mechanism ◽  
Metal Layer ◽  
Noise Margin ◽  
Soft Failure ◽  
Sram Cell ◽  
Cell Stability ◽  
The Stability ◽  
Static Noise

Abstract This paper presents the process of measuring static noise margin (SNM), write noise margin (WNM) with 6 pin nanoprober, and characterization and analysis of SRAM cell stability through case studies of 45nm devices SRAM soft failures. It highlights that the local mismatch in the bit cell caused by slight variations in the transistor characteristics, such as Vth shift and Idsat, off variation, also can easily induce a soft failure. The analysis of the SNM TR characteristic is successfully demonstrated through the case study of 45nm SRAM devices. The chapter explains SNM measurement in the metal layer and transistor measurements in the CA layer. Measuring the SNM TR's characteristics is an important methodology in understanding the stability of each bit cell and failure mechanism depending on voltage, defects, and other factors. The next generation of nanoprobing analysis can be expanded.

Humidity-Bias Driven Shorts in Multilayer Circuits: A Case Study in Failure Analysis

2000 ◽  
Author(s):  
Hei-Ruey Harry Jen ◽  
Gerald S. D’Urso ◽  
Harold Andrews
Keyword(s):  
Failure Analysis ◽  
Failure Mechanism ◽  
Layer Structure ◽  
Molding Compound ◽  
Plastic Molding ◽  
Root Cause ◽  
Plastic Package ◽  
Processing Procedure ◽  
Failure Site

Abstract When a failure analysis (FA) involves a multiple layer structure separated by a polymeric material such as Benzocyclobutene (BCB), in a plastic package, it becomes a very challenging task to find out where the failure site is and how it failed. This is due to the fact that the chemical de-processing procedure removes BCB as well as the plastic molding compound. This paper outlines the studies carried out to determine the failure site and the root cause of the failure mechanism in a multilayer circuit and the steps taken to fix the problems. The methodology and results of this study are applicable to many other types of circuits.

Verification of DLS Data by LVP in Case of Marginal Failure

2016 ◽  
Author(s):  
Keonil Kim ◽  
Sungjin Kim ◽  
Kunjae Lee ◽  
Kyeongju Jin ◽  
Yunwoo Lee ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Failure Mechanism ◽  
Fault Location ◽  
Photon Emission ◽  
Fault Localization ◽  
Fault Isolation ◽  
The Real ◽  
Defect Isolation ◽  
The Relationship ◽  
Non Destructive

Abstract In most of the non-destructive electrical fault isolation cases, techniques such as DLS, Photon Emission, LIT, OBIRCH indicate a fault location directly. But relying on just one of these techniques for marginal failure mechanism is not enough for better fault localization. When Failure Analysis (FA) engineers encounter high NDF (No Defect Found) rates, by using only one of the techniques, they may need to consider the relationship between the responded locations by different techniques and fail phenomenon for better defect isolation. This paper talks about how a responded DLS location does not always indicate a fault location and how LVP data collected using DLS location can pin point the real defect location.

Multi-Level Approach for High-Precision Cache Fault Isolation—Case Study: Itanium® II Processor Low Voltage Cache Yield Improvement

2004 ◽  
Author(s):  
Chia Ling Kong ◽  
Mohammed R. Islam
Keyword(s):  
Failure Analysis ◽  
Fault Location ◽  
Low Voltage ◽  
Circuit Simulation ◽  
Physical Structure ◽  
Fault Isolation ◽  
Embedded Memory ◽  
Yield Improvement ◽  
Multi Level

Abstract Fault Isolation / Failure Analysis (FI/FA) of increasingly complex embedded memory in microprocessors is becoming more difficult due to process scaling and presence of subtle defects. As physical failure analysis (PFA) is destructive and involves expensive and time-consuming processes, fault diagnosis needs to be as precise as possible to ensure successful physical defect sighting. This paper introduces a cache Fault Isolation methodology that focuses on exhaustive data collection to derive concrete hypothesis of physical fault location and to overcome the existing FA/FI challenges. The methodology involves a novel application of existing DFT techniques in combination with circuit analysis, pattern hacking, defect localization and PFA tools. Some of the techniques, for example pattern modification or circuit simulation, are applied repeatedly in order to obtain higher-level of isolation – from cell/logic level to transistor/gate level, and finally down to physical structure/layer level. This multi-level FI approach is the key to localize the failing area to greater precision, which had proven itself in Intel Itanium® II processor yield improvement process.

A Logical Problem Solving Process for High Via Resistance Root Cause Analysis

2008 ◽  
Author(s):  
K. Li ◽  
P. Liu ◽  
J. Teong ◽  
M. Lee ◽  
H. L. Yap
Keyword(s):  
Problem Solving ◽  
Failure Analysis ◽  
Failure Mechanism ◽  
High Resistance ◽  
Cause Analysis ◽  
Logical Problem ◽  
Root Cause ◽  
Analysis Process ◽  
Problem Solving Process

Abstract This paper presents a case study on via high resistance issue. A logical failure analysis process EDCA (Effect, Defect, Cause, and Action) is successfully applied to find out the failure mechanism, pinpoint the root cause and solve the problem. It sets up a very good example of how to do tough failure analysis in a controllable way.

scholarly journals Failure Analysis of a Half-Micron CMOS IC Technology

1996 ◽  
Author(s):  
A.Y. Liang ◽  
P. Tangyunyong ◽  
R.S. Bennett ◽  
R.S. Flores ◽  
J.M. Soden ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Photon Emission ◽  
Deposition Process ◽  
Cmos Technology ◽  
Contrast Imaging ◽  
Wafer Processing ◽  
Voltage Contrast ◽  
Tools And Techniques

Abstract We present the results of recent failure analysis of an advanced, 0.5 um, fully planarized, triple metallization CMOS technology. A variety of failure analysis (FA) tools and techniques were used to localize and identify defects generated by wafer processing. These include light (photon) emission microscopy (LE), fluorescent microthermal imaging (FMI), focused ion beam cross sectioning, SEM/voltage contrast imaging, resistive contrast imaging (RCI), and e-beam testing using an IDS-5000 with an HP 82000. The defects identified included inter- and intra-metal shorts, gate oxide shorts due to plasma processing damage, and high contact resistance due to the contact etch and deposition process. Root causes of these defects were determined and corrective action was taken to improve yield and reliability.

Stacked Polysilicon/Metal Capacitors Failure Analysis

2005 ◽  
Author(s):  
Dat T. Nguyen ◽  
Frank Huang
Keyword(s):  
Liquid Crystal ◽  
Failure Analysis ◽  
Fault Isolation ◽  
Visual Defect ◽  
Capacitor Plate ◽  
Chemical Etch ◽  
Defect Localization ◽  
Voltage Contrast

Abstract Poly/metal stacked capacitors present challenges in terms of capacitor access and defect localization. As for defect localization, liquid crystal or thermal localization (also OBIRCH/TIVA) and passive voltage contrast (PVC) are used. PVC was found to be effective in terms of finding the bad stacked capacitor and a bad capacitor within the stack. This paper highlights brief process steps in 3-layer polysilicon/metal stacked capacitors. It discusses FA on stacked capacitors, providing information on fault isolation and capacitor access. It presents a case study on differentiating defective capacitors which failing due to vertical shorting. Internal probing between the capacitors within a stack allowed the differentiation between capacitor leakage and capacitor-capacitor shorting. For capacitor leakage, the defect can be identified by parallel lapping to remove the upper capacitor plate. For capacitor-capacitor short, if there is no visual defect seen, Pt chemical etch can be applied for PVC inspection.

Failure Analysis Case Study of Inductively Coupled Cross-Chip Signals

2016 ◽  
Author(s):  
Steven Loveless ◽  
Zhihong You ◽  
Tathagata Chatterjee ◽  
Badarish Subbannavar
Keyword(s):  
Failure Analysis ◽  
Failure Mechanism ◽  
Individual Data ◽  
Cause Analysis ◽  
Inductively Coupled ◽  
Root Cause ◽  
Specific Device ◽  
Data Points ◽  
On Chip

Abstract This paper discusses a failure analysis case study in a highly integrated mixed signal device caused by inductive coupling of on-chip signals. The techniques utilized and the approach to root cause analysis are discussed in depth. The interactions between the device design and failure mechanism are identified in detail. Focus is placed on drawing conclusions from the sum of individual data points, and the discussion provides an analytical path by which similar failures can be isolated and specific device sensitivities can be identified.

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