Process Flow Employed for Parametric Test Structure Chain Opens Fault Isolation in 20 nm and Sub-20 nm Technologies in High Throughput Foundries

2016 ◽  
Author(s):  
Satish Kodali ◽  
Yinzhe Ma ◽  
Chong Khiam Oh ◽  
Wayne Zhao ◽  
Felix Beaudoin
Keyword(s):  
Cross Sections ◽  
Process Development ◽  
Fault Isolation ◽  
Flow Sheet ◽  
Process Flow ◽  
Parametric Test ◽  
Root Cause ◽  
Voltage Contrast ◽  
Root Cause Identification ◽  
20 Nm

Abstract With increasing complexity involved in advance node semiconductor process development, dependability on parametric test structures has also increased significantly. Test structures play a predominant role throughout the entire development cycle of a product. They are used to understand the process windows and also help to monitor the health of a line. This work provides a process flow sheet for root cause identification on chain opens on advanced 20 nm and sub-20 nm technologies setting a standard guideline for a specific category fail type. It provides a consistent way of attack in a much more streamlined fashion. Further, dependability on TEM rather than convention FIB cross-sections provides shortest time to root cause identification. Three typical cases encountered are discussed to demonstrate the idea: embedded chain opens by electron beam absorbed current (EBAC) isolation, chains opens at level by EBAC isolation, and chains opens at level by passive voltage contrast isolation.

Process Flow Employed for Parametric Test Structure Shorts Fault Isolation in 20 nm and Sub-20 nm Technologies in High Throughput Foundries

2017 ◽  
Author(s):  
Satish Kodali ◽  
Mia Nasimullah ◽  
Yuting Wei ◽  
Chong Khiam Oh ◽  
Felix Beaudoin
Keyword(s):  
Process Development ◽  
Fault Isolation ◽  
Predominant Role ◽  
Process Flow ◽  
Parametric Test ◽  
Root Cause ◽  
Development Cycle ◽  
Root Cause Identification ◽  
20 Nm ◽  
Low K

Abstract With increasing complexity involved in advance node semiconductor process development, dependability on parametric test structures has also increased significantly. Test structures play a predominant role throughout the entire development cycle of a product. It becomes very important to understand the root cause of failures at fastest pace to take necessary corrective actions. The use of ultra low K dielectrics for back end of line wafer build for advanced nodes created significant constraints on conventional beam imaging methods for fault isolation. This paper provides a streamlined process flow for root cause identification on shorts on advanced 20 nm and sub-20 nm technologies. Three unique cases are presented to demonstrate three typical situations identified in the process flow. They are blown capacitors, gate leakage, and resistance ladder short isolation.

Utilizing Nanoprobing and Circuit Diagnostics to Identify Key Failure Mechanism of Otherwise Nonvisible Defects in 20 nm Logic Devices

2014 ◽  
Author(s):  
M.K. Dawood ◽  
C. Chen ◽  
P.K. Tan ◽  
S. James ◽  
P.S. Limin ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Contact Layer ◽  
Fault Isolation ◽  
Tem Analysis ◽  
Logic Devices ◽  
Technology Advancement ◽  
Transmission Electron ◽  
Voltage Contrast ◽  
Almost All ◽  
20 Nm

Abstract In this work, we present two case studies on the utilization of advanced nanoprobing on 20nm logic devices at contact layer to identify the root cause of scan logic failures. In both cases, conventional failure analysis followed by inspection of passive voltage contrast (PVC) failed to identify any abnormality in the devices. Technology advancement makes identifying failure mechanisms increasingly more challenging using conventional methods of physical failure analysis (PFA). Almost all PFA cases for 20nm technology node devices and beyond require Transmission Electron Microscopy (TEM) analysis. Before TEM analysis can be performed, fault isolation is required to correctly determine the precise failing location. Isolated transistor probing was performed on the suspected logic NMOS and PMOS transistors to identify the failing transistors for TEM analysis. In this paper, nanoprobing was used to isolate the failing transistor of a logic cell. Nanoprobing revealed anomalies between the drain and bulk junction which was found to be due to contact gouging of different severities.

An Effective Failure Analysis Strategy for the Successful Introduction of New Products Designed in 90 and 65 nm CMOS Technologies

2004 ◽  
Author(s):  
F. Lorut ◽  
M. Lamy ◽  
M. de la Bardonnie ◽  
S. Fabre ◽  
R. Ross ◽  
...  
Keyword(s):  
Failure Analysis ◽  
New Products ◽  
Fault Isolation ◽  
Physical Characterization ◽  
Parametric Test ◽  
Process Improvements ◽  
Characterization Techniques ◽  
Analysis Strategy ◽  
Voltage Contrast

Abstract IC manufacturers, among other things, have to define a global failure analysis (FA) strategy that is best adopted to the challenges associated to the introduction of the 90 and 65 nm CMOS technologies. This article reviews the existing FA techniques and then describes an FA strategy that is aiming at fast, efficient, and economic learning in the latest 120-65 nm CMOS technologies. The strategy is based on a well-balanced mix and usage of in-line defectivity data, voltage contrast analyses, SRAM bitmap analysis results, OBIRCH fault isolation, and various advanced physical characterization techniques. A SRAM bitmap strategy has demonstrated to be very effective in driving most relevant process improvements, and also OBIRCH applied to parametric test structures has helped significantly in identifying major yield detractors.

Fast Root Cause Identification Using Combination of Failure Analysis and In-Line Inspection

2017 ◽  
Author(s):  
Zhigang Song ◽  
Weihao Weng ◽  
Brett Engel
Keyword(s):  
Failure Analysis ◽  
Process Development ◽  
Second Step ◽  
Line Defect ◽  
Semiconductor Technology ◽  
Process Step ◽  
Root Cause ◽  
The Past ◽  
Root Cause Identification ◽  
The Relationship

Abstract Failure analysis plays an important role in yield improvement during semiconductor process development and device manufacturing. It includes two main steps. The first step is to find the defect and the second step is to identify the root cause. In the past, failure analysis mainly focused on the first step, namely how to find the defect for a failure; because in the previous generations of technology, once the defect was found, its root cause was relatively easy to be understood. As the current advanced semiconductor technology has become tremendously complicated, especially 3D devices, like FinFET, a defect found by failure analysis can be substantially transformed from its original defect by subsequent processes and can be totally different from its origin in size and shape. Thus, sometimes, the second step, identifying the root cause for a defect becomes more challenging and takes more time than the first step. With combination of failure analysis and inline inspection, it enables us to establish the relationship between the failure analysis defect and an in-line defect. This can link the defect for a device functional failure to its source layer and process step more quickly, leading to fast root cause identification. In this paper, the methodology was validated by fast identification of the root causes for three case studies in the latest FinFET technology.

Laser Voltage Probing in Failure Analysis of Advanced Integrated Circuits on SOI

2012 ◽  
Author(s):  
V.K. Ravikumar ◽  
R. Wampler ◽  
M.Y. Ho ◽  
J. Christensen ◽  
S.L. Phoa
Keyword(s):  
Integrated Circuits ◽  
Failure Analysis ◽  
Case Studies ◽  
Timing Analysis ◽  
Fault Isolation ◽  
Root Cause ◽  
Root Cause Identification

Abstract Laser voltage probing is the newest generation of tools that perform timing analysis for electrical fault isolation in advanced failure analysis facilities. This paper uses failure analysis case studies on SOI to showcase the implementation of laser voltage probing in the failure analysis flow and highlight its significance in root-cause identification.

Unique Approaches to Isolate Nanoscale Defect in Snake-Comb Test Structure

2015 ◽  
Author(s):  
Sujing Xie ◽  
Nathan Wang ◽  
Chaoying Chen ◽  
Qindi Wu
Keyword(s):  
Failure Analysis ◽  
Electrical Resistance ◽  
Test Structure ◽  
Yield Enhancement ◽  
Nanometer Scale ◽  
Cross Sectional ◽  
Root Cause ◽  
Unique Approach ◽  
Voltage Contrast ◽  
Root Cause Identification

Abstract Multiple techniques including electrical resistance measurement plus calculation, cross-sectional view of passive voltage contrast (XPVC) sequential searching, planar and cross-section STEM are successfully used to isolate a nanoscale defect, single metallic stringer in a snakecomb test structure. The defect could not be found by traditional failure analysis methods or procedures. The unique approach presented here, expands failure analysis capabilities to the detection of nanometer-scale defects and the identification of their root causes. With continuous shrinking feature sizes, the need of such techniques becomes more vital to failure analysis and root cause identification, and therefore yield enhancement in fabrication.

Fault Isolation of MOL and FEOL Buried Defects Using Conductive Atomic Force Microscopy as a Complement to Passive Voltage Contrast Imaging

2017 ◽  
Author(s):  
Lucile C. Teague Sheridan ◽  
Linda Conohan ◽  
Chong Khiam Oh
Keyword(s):  
Atomic Force Microscopy ◽  
Cmos Technology ◽  
Fault Isolation ◽  
Contrast Imaging ◽  
Conductive Atomic Force Microscopy ◽  
Isolation Technique ◽  
Conductive Afm ◽  
Force Microscopy ◽  
Atomic Force ◽  
Voltage Contrast

Abstract Atomic force microscopy (AFM) methods have provided a wealth of knowledge into the topographic, electrical, mechanical, magnetic, and electrochemical properties of surfaces and materials at the micro- and nanoscale over the last several decades. More specifically, the application of conductive AFM (CAFM) techniques for failure analysis can provide a simultaneous view of the conductivity and topographic properties of the patterned features. As CMOS technology progresses to smaller and smaller devices, the benefits of CAFM techniques have become apparent [1-3]. Herein, we review several cases in which CAFM has been utilized as a fault-isolation technique to detect middle of line (MOL) and front end of line (FEOL) buried defects in 20nm technologies and beyond.

A New Failure Analysis Flow of Gate Oxide Integrity Failure in Wafer Fabrication

2009 ◽  
Author(s):  
Hua Younan ◽  
Chu Susan ◽  
Gui Dong ◽  
Mo Zhiqiang ◽  
Xing Zhenxiang ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Gate Dielectric ◽  
Dielectric Breakdown ◽  
Defect Density ◽  
Gate Oxide ◽  
Oxide Thickness ◽  
Fault Isolation ◽  
Wafer Fabrication ◽  
Root Cause ◽  
Gate Oxide Integrity

Abstract As device feature size continues to shrink, the reducing gate oxide thickness puts more stringent requirements on gate dielectric quality in terms of defect density and contamination concentration. As a result, analyzing gate oxide integrity and dielectric breakdown failures during wafer fabrication becomes more difficult. Using a traditional FA flow and methods some defects were observed after electrical fault isolation using emission microscopic tools such as EMMI and TIVA. Even with some success with conventional FA the root cause was unclear. In this paper, we will propose an analysis flow for GOI failures to improve FA’s success rate. In this new proposed flow both a chemical method, Wright Etch, and SIMS analysis techniques are employed to identify root cause of the GOI failures after EFA fault isolation. In general, the shape of the defect might provide information as to the root cause of the GOI failure, whether related to PID or contamination. However, Wright Etch results are inadequate to answer the questions of whether the failure is caused by contamination or not. If there is a contaminate another technique is required to determine what the contaminant is and where it comes from. If the failure is confirmed to be due to contamination, SIMS is used to further determine the contamination source at the ppm-ppb level. In this paper, a real case of GOI failure will be discussed and presented. Using the new failure analysis flow, the root cause was identified to be iron contamination introduced from a worn out part made of stainless steel.

Application of KOH Electrochemical Etch and Passive Voltage Contrast Techniques for Deep Sub-Micron CMOS Leaky Gate Detection

2000 ◽  
Author(s):  
Fred Y. Chang ◽  
Victer Chan
Keyword(s):  
Case Studies ◽  
Detection Technique ◽  
Cobalt Silicide ◽  
Process Technology ◽  
Process Flow ◽  
Voltage Contrast ◽  
Emission Detection ◽  
Wet Etch ◽  
Direct Confirmation

Abstract This paper describes a novel de-process flow by combining cobalt silicide / nitride wet etch with KOH electrochemical wet etch (ECW) to identify leaky gate in silicided deep sub-micron process technology. Traditionally, leaky gate identification requires direct confirmation by gate level electrical or emission detection technique. Ohtani [1] used KOH electrochemical etch application to identify nonsilicided leaky gate capacitor in DRAM without using the above confirmation. The result of the case study demonstrates the expanded application of ECW etch to both silicided 0.18um logic and SRAM devices. Voltage contrast at metal 1 to assist leaky gate localization is also proposed. By combining both techniques, the possibility for isolating gate related defects are greatly enhanced. Case studies also show the advantages of the proposed technique over conventional poly level voltage contrast in leaky gate identification especially with devices that use local interconnect and nitride liner process.

Application of Scan Based FA and Advanced Passive Voltage Contrast Technique in Defect Isolation

2003 ◽  
Author(s):  
Michael B. Schmidt ◽  
Noor Jehan Saujauddin
Keyword(s):  
Failure Analysis ◽  
Large Scale ◽  
Fault Isolation ◽  
Electronic Information ◽  
Scan Testing ◽  
Challenging Environment ◽  
Contrast Technique ◽  
Defect Isolation ◽  
Voltage Contrast ◽  
Higher Sensitivity

Abstract Scan testing and passive voltage contrast (PVC) techniques have been widely used as failure analysis fault isolation tools. Scan diagnosis can narrow a failure to a given net and passive voltage contrast can give real-time, large-scale electronic information about a sample at various stages of deprocessing. In the highly competitive and challenging environment of today, failure analysis cycle time is very important. By combining scan FA with a much higher sensitivity passive voltage contrast technique, one can quickly find defects that have traditionally posed a great challenge.

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