scholarly journals An Energy-Efficient Strategy for Microcontrollers

2021 ◽  
Vol 11 (6) ◽  
pp. 2581
Author(s):  
Huanjie Wu ◽  
Chun Chen ◽  
Kai Weng
Keyword(s):  
Energy Efficiency ◽  
Power Consumption ◽  
Low Power ◽  
Power Saving ◽  
Research Direction ◽  
Sleep Time ◽  
Analytical Models ◽  
Clock Frequency ◽  
Improve Energy Efficiency ◽  
Time Required

Power saving has always been an important research direction in the field of microcontrollers. Dozens of low power technologies have been proposed to achieve the goal of reducing their power consumption. However, most of them focus mostly on lowering the consumption rate. It is well known that energy is the integral of power over time. Thus, our view is that both power and time should be carefully considered to achieve better energy efficiency. We reviewed some commonly used low power technologies and proposed our assumptions and strategy for improving energy efficiency. A series of test sets are designed to validate our hypotheses for improving energy efficiency. The experimental results suggest that time has no less impact on energy consumption than power. To support the operation of the processor, some peripheral components consume a constant amount of power regardless of the clock frequency, but the power consumption will be reduced when the processor enters low-power modes. This results in some interesting phenomena that are different from the usual thinking that energy can be saved by increasing processor clock frequency. For STM32F407 and Xtensa LX6 processors, this article also analyzes and calculates the minimum sleep time required for achieving energy saving based on our analytical models. Our energy efficiency strategy has been verified, and in some cases, it can indeed improve energy efficiency. We also proposed some suggestions on hardware design and software development for better energy efficiency.

scholarly journals Power Saving Proxies for Web Servers

2019 ◽  
Vol 63 (2) ◽  
pp. 179-192
Author(s):  
Karl J O’Dwyer ◽  
Eoin Creedon ◽  
Mark Purcell ◽  
David Malone
Keyword(s):  
Energy Efficiency ◽  
Power Consumption ◽  
Embedded System ◽  
Power Saving ◽  
Web Servers ◽  
Small Energy ◽  
Significant Percentage ◽  
Improve Energy Efficiency ◽  
Data Centre ◽  
Energy Footprint

Abstract Electricity is a major cost in running a data centre, and servers are responsible for a significant percentage of the power consumption. Given the widespread use of HTTP, both as a service and a component of other services, it is worthwhile reducing the power consumption of web servers. In this paper we consider how reverse proxies, commonly used to improve the performance of web servers, might be used to improve energy efficiency. We suggest that when demand on a server is low, it may be possible to switch off servers. In their absence, an embedded system with a small energy footprint could act as a reverse proxy serving commonly-requested content. When new content is required, the reverse proxy can power on the servers to meet this new load. Our results indicate that even with a modest server, we can get a 25% power saving while maintaining acceptable performance.

LOW POWER ADIABATIC PROGRAMMABLE LOGIC ARRAY WITH SINGLE CLOCK IAPDL

2008 ◽  
Vol 17 (02) ◽  
pp. 211-219
Author(s):  
W. J. YANG ◽  
Y. ZHOU ◽  
K. T. LAU
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Power Saving ◽  
Programmable Logic ◽  
Clock Frequency ◽  
Programmable Logic Array ◽  
Simulation Results ◽  
Critical Components ◽  
Logic Array ◽  
Single Power

A novel implementation of a low power adiabatic PLA with a single power clock (IAPDL-SC PLA) is presented. The isolation transistor in the AND array is removed. The power clock is shared by the AND array and the OR array. In this way, the proposed PLA not only saves the device components but also reduces the power consumption. For 3 V VDD and 200 MHz power clock frequency, the simulation results using Hspice show that the power saving is 79.48% compared to dynamic CMOS PLA, 69.34% compared to APDL PLA, and 40.40% compared to IAPDL PLA. For the 5 × 8 × 4 PLA design, the device saving is 30.77% compared to APDL PLA and 12.90% compared to IAPDL PLA. The diodes are the critical components for all the technology designs. Current simulation is based on 0.8 μm process and the power consumption can be further reduced using the more downsized technology designs.

scholarly journals Massive MIMO: Achievable Energy Efficiency for 5G systems with Multi-user Environment

2019 ◽  
Vol 8 (2) ◽  
pp. 6527-6534
Keyword(s):  
Energy Efficiency ◽  
Power Consumption ◽  
Path Loss ◽  
Antenna System ◽  
Base Station ◽  
Small Cells ◽  
Limiting Factors ◽  
Improve Energy Efficiency ◽  
User Terminal ◽  
Simulation Results

Massive Multi-Input and Multi-Output (MIMO) antenna system potentially provides a promising solution to improve energy efficiency (EE) for 5G wireless systems. The aim of this paper is to enhance EE and its limiting factors are explored. The maximum EE of 48 Mbit/Joule was achieved with 15 user terminal (UT)s. This problem is related to the uplink spectral efficiency with upper bound for future wireless networks. The maximal EE is obtained by optimizing a number of base station (BS) antennas, pilot reuse factor, and BSs density. We presented a power consumption model by deriving Shannon capacity calculations with closed-form expressions. The simulation result highlights the EE maximization with optimizing variables of circuit power consumption, hardware impairments, and path-loss exponent. Small cells achieve high EE and saturate to a constant value with BSs density. The MRC scheme achieves maximum EE of 36 Mbit/Joule with 12 UTs. The simulation results show that peak EE is obtained by deploying massive BS antennas, where the interference and pilot contamination are mitigated by coherent processing. The simulation results were implemented by using MATLAB 2018b.

scholarly journals A Glitch-Free Novel DET-FF in 22 nm CMOS for Low-Power Application

2018 ◽  
Vol 2018 ◽  
pp. 1-6 ◽  
Author(s):  
Sumitra Singar ◽  
N. K. Joshi ◽  
P. K. Ghosh
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Performance ◽  
Vlsi Design ◽  
Total System ◽  
Clock Frequency ◽  
Flip Flop ◽  
Digital Vlsi ◽  
Feedback Structure ◽  
Power Application

Dual edge triggered (DET) techniques are most liked choice for the researchers in the field of digital VLSI design because of its high-performance and low-power consumption standard. Dual edge triggered techniques give the similar throughput at half of the clock frequency as compared to the single edge triggered (SET) techniques. Dual edge triggered techniques can reduce the 50% power consumption and increase the total system power savings. The low-power glitch-free novel dual edge triggered flip-flop (DET-FF) design is proposed in this paper. Still now, existing DET-FF designs are constructed by using either C-element circuit or 1P-2N structure or 2P-1N structure, but the proposed novel design is designed by using the combination of C-element circuit and 2P-1N structure. In this design, if any glitch affects one of the structures, then it is nullified by the other structure. To control the input loading, the two circuits are merged to share the transistors connected to the input. In the proposed design, we have used an internal dual feedback structure. The proposed design reduces the delay and power consumption and increases the speed and efficiency of the system.

scholarly journals The Numerical Simulation of the Airflow Distribution and Energy Efficiency in Data Centers with Three Types of Aisle Layout

2019 ◽  
Vol 11 (18) ◽  
pp. 4937 ◽  
Author(s):  
Jing Ni ◽  
Bowen Jin ◽  
Shanglei Ning ◽  
Xiaowei Wang
Keyword(s):  
Energy Efficiency ◽  
Power Consumption ◽  
Air Conditioning ◽  
Data Centers ◽  
Simulation Method ◽  
Cooling Capacity ◽  
Energy Utilization ◽  
Improve Energy Efficiency ◽  
Electricity Cost ◽  
Airflow Distribution

The energy consumption of fast-growing data centers is drawing attentions from not only energy organizations and institutions all over the world, but also charity groups, such as Greenpeace, and research shows that the power consumption of air conditioning makes up a large proportion of the electricity cost in data centers. Therefore, more detailed investigations of air conditioning power consumption are warranted. Three types of airflow distributions with different aisle layouts (the open aisle, the closed cold aisle, and the closed hot aisle) were investigated with Computational Fluid Dynamics (CFD) methods in a typical data center of four rows of racks in this study. To evaluate the results of thermal and bypass phenomenon, the temperature increase index (β) and the energy utilization index (ηr) were used. The simulations show that there is a better trend of the β index and ηr index both closed cold aisle and closed hot aisle compared with free open aisle. Especially with high air flow rate, the β index decreases and the ηr index increases considerably. Moreover, the results prove the closed aisles (both closed cold aisle and closed hot aisle) can not only significantly improve the airflow distribution, but also reduce the mixture of cold and heat flow, and therefore improve energy efficiency. In addition, it proves the design of the closed aisles can meet the increasing density of installations and our simulation method could evaluate the cooling capacity easily.

scholarly journals Improving Energy Efficiency in Idle Listening of IEEE 802.11 WLANs

2016 ◽  
Vol 2016 ◽  
pp. 1-15 ◽  
Author(s):  
Muhammad Adnan ◽  
Eun-Chan Park
Keyword(s):  
Energy Efficiency ◽  
Ieee 802.11 ◽  
Power Saving ◽  
Local Area ◽  
Contention Window ◽  
Channel Access ◽  
Analysis Model ◽  
Frame Aggregation ◽  
Improve Energy Efficiency ◽  
Idle Listening

This paper aims to improve energy efficiency of IEEE 802.11 wireless local area networks (WLANs) by effectively dealing with idle listening (IL), which is required for channel sensing and is unavoidable in a contention-based channel access mechanism. Firstly, we show that IL is a dominant source of energy drain in WLANs and it cannot be effectively alleviated by the power saving mechanism proposed in the IEEE 802.11 standard. To solve this problem, we propose an energy-efficient mechanism that combines three schemes in a systematic way: downclocking, frame aggregation, and contention window adjustment. The downclocking scheme lets a station remain in a semisleep state when overhearing frames destined to neighbor stations, whereby the station consumes the minimal energy without impairing channel access capability. As well as decreasing the channel access overhead, the frame aggregation scheme prolongs the period of semisleep time. Moreover, by controlling the size of contention window based on the number of stations, the proposed mechanism decreases unnecessary IL time due to collision and retransmission. By deriving an analysis model and performing extensive simulations, we confirm that the proposed mechanism significantly improves the energy efficiency and throughput, by up to 2.8 and 1.8 times, respectively, compared to the conventional power saving mechanisms.

scholarly journals Low Power Checks in Multi Voltage Designs

2020 ◽  
Vol 11 ◽  
pp. 105-111
Author(s):  
K. R. Haripriya ◽  
Ajay Somkuwar ◽  
Laxmi Kumre
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Semiconductor Industry ◽  
Power Saving ◽  
Critical Issue ◽  
Leakage Power ◽  
Design Flow ◽  
Power Gating ◽  
Low Power Architectures

Leakage power consumption has been almost a serious problem these days in semiconductor industry. Many low power techniques like multi-voltage, power gating etc. are deployed to improve power saving. Power aware verification hence has become a critical issue now. Static low power verification has been developed to verify that low power architectures are designed in correct approach meeting all electrical rules in SoC. The UPF(Unified Power Format) is the standardized format that has all power intent information and can be used throughout the design flow to ensure that the power specification is intact. Firstly, this paper describes the special cells and its operation used in low power techniques. Secondly it describes the major checks examined at each stage using Synopsys VCLP tool and finally debugging with the tool and conclusion.

scholarly journals Cell Throughput based Sleep Control Scheme for Heterogeneous Cellular Networks

2018 ◽  
Vol 12 (1) ◽  
pp. 26-33
Author(s):  
Prapassorn Phaiwitthayaphorn ◽  
Kazuo Mori ◽  
Hideo Kobayashi ◽  
Pisit Boonsrimuang
Keyword(s):  
Energy Efficiency ◽  
Power Consumption ◽  
Cellular Networks ◽  
Operating Cost ◽  
Reducing Power ◽  
Network Capacity ◽  
Base Station ◽  
Base Stations ◽  
Improve Energy Efficiency ◽  
Sleep Control

The mobile traffic continuously grows at a rapid rate driven by the widespread use of wireless devices. Along with that, the demands for higher data rate and better coverage lead to increase in power consumption and operating cost of network infrastructure. The concept of heterogeneous networks (HetNets) has been proposed as a promising approach to provide higher coverage and capacity for cellular networks. HetNet is an advanced network consisting of multiple kinds of base stations, i.e., macro base station (MBS), and small base station (SBS). The overlay of many SBSs into the MBS coverage can provide higher network capacity and better coverage in cellular networks. However, the dense deployment of SBSs would cause an increase in the power consumption, leading to a decrease in the energy efficiency in downlink cellular networks. Another technique to improve energy efficiency while reducing power consumption in the network is to introduce sleep control for SBSs. This paper proposes cell throughput based sleep control which the cell capacity ratio for the SBSs is employed as decision criteria to put the SBSs into a sleep state. The simulation results for downlink communications demonstrate that the proposed scheme improves the energy efficiency, compared with the conventional scheme.

Low-Power Consumption Light-stimulated Synaptic Transistors Based on Natural Carotene and Organic Semiconductors

2021 ◽  
Author(s):  
Ben Yang ◽  
Yan Wang ◽  
Zhekun Hua ◽  
Junyao Zhang ◽  
Li Li ◽  
...  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Organic Semiconductors ◽  
Research Direction ◽  
Low Power Consumption ◽  
Environmental Friendly

Developing synaptic devices with environmental-friendly materials is a promising research direction. Here, light-stimulated synaptic transistors based on natural carotene and organic semiconductors were developed. Several important functions similar to biological...

The Study on Power Consumption Models for Low-Power Wireless Communications

2011 ◽  
Vol 268-270 ◽  
pp. 1691-1696
Author(s):  
Xiao Ling Mo ◽  
Mei Xiang Peng
Keyword(s):  
Energy Efficiency ◽  
Wireless Communications ◽  
Power Consumption ◽  
Low Power ◽  
Path Loss ◽  
Energy Consumption Optimization ◽  
Channel Loss ◽  
Transmission Energy Consumption ◽  
Transmission Energy ◽  
Efficiency Consideration

Power consumption models for low-power wireless communications, where transmitter and receiver electronics power consumption is comparable to PA power consumption, are based on channel path loss, depending on distance between transmitter and receiver, making them suitable for energy-efficiency consideration of multi-hop vs. single-hop communication. We propose L – model, based on total channel-loss, that is more suitable for transmission energy consumption optimization in the sense of different modulation and coding techniques than d – models. Since total channel loss information is available at current transceivers in terms of RSSI and LQI, L – model is more suitable for TPC techniques optimization than d – models.

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