scholarly journals A Pipeline-TDC-Based CMOS Temperature Sensor with a 48 fJ·K2 Resolution FoM

Electronics ◽  
2021 ◽  
Vol 10 (13) ◽  
pp. 1542
Author(s):  
Zhikuang Cai ◽  
Ze Wang ◽  
Wenjing Zhang ◽  
Xin Wang ◽  
Zixuan Wang
Keyword(s):  
Temperature Sensor ◽  
Energy Efficient ◽  
Figure Of Merit ◽  
Average Power ◽  
Cmos Technology ◽  
Duty Cycling ◽  
Chip Area ◽  
Conversion Time ◽  
Programmable Gain ◽  
Time Amplifier

An energy-efficient temperature sensor is important for temperature monitoring in Biomedical Internet-of-things (BIoT) applications. This article presents a time-domain temperature sensor with a pipeline time-to-digital converter (TDC). A programmable-gain time amplifier (PGTA) with high linearity and wide linear range is proposed to improve the resolution of the sensor and to reduce the chip area. The conversion time of the sensor is reduced by the fast TDC that only needs ~26 ns/conversion, which means the sensor is suitable for BIoT applications that commonly use duty cycling mode. Fabricated in a 40 nm standard CMOS technology, the sensor consumes 7.6 μA at a 0.6 V supply and achieves a resolution of 90 mK and a sensitivity of 0.62%/°C in a 1.3 μs conversion time. This translates into a resolution figure-of-merit of 48 fJ·K2. The sensor achieves an inaccuracy of 0.39 °C from −20 °C to 80 °C after two-point calibration. Duty cycling the sensor results in an even lower average power: ~18.6 nW at 10 conversions/s.

Energy-Efficient and Area-Efficient QC-LDPC with RS Decoders Using 2M-LMSA

2014 ◽  
Vol 24 (02) ◽  
pp. 1550026 ◽  
Author(s):  
Chang-Kun Yao ◽  
Yun-Ching Tang ◽  
Hongchin Lin
Keyword(s):  
Energy Efficient ◽  
Communication Systems ◽  
Average Power ◽  
Ldpc Code ◽  
Cmos Technology ◽  
Clock Frequency ◽  
Hardware Complexity ◽  
Chip Area ◽  
Ldpc Decoder ◽  
Area Efficient

This study proposes an energy-efficient and area-efficient dual-path low-density parity-check (LDPC) with Reed–Solomon (RS) decoder for communication systems. Hardware complexity is reduced by applying a dual-path 2-bit modified layered min-sum algorithm (2M-LMSA) to a (2550, 2040) quasi-cyclic LDPC (QC-LDPC) code with the column and row weights of 3 and 15, respectively. The simplified check node units (CNUs) reduce memory and routing complexity as well as the energy needed to decode each bit. A throughput of 11 Gb/s is achieved by using 90-nm CMOS technology at a clock frequency of 208 MHz at 0.9 V with average power of 244 mW on a chip area of 3.05 mm2. Decoding performance is further improved by appending the (255, 239) RS decoder after the LDPC decoder. The LDPC plus RS decoder consumes the power of 434 mW on the area of 3.45 mm2.

A CMOS Temperature Sensor with a Maximum Accuracy of 1.6 °C after One-Point Calibration

2013 ◽  
Vol 336-338 ◽  
pp. 216-220
Author(s):  
Chun Chi Chen ◽  
Keng Chih Liu ◽  
Shih Hao Lin
Keyword(s):  
Temperature Sensor ◽  
Pulse Generator ◽  
Circuit Complexity ◽  
Absolute Temperature ◽  
Cmos Process ◽  
Chip Area ◽  
Test Cost Reduction ◽  
Linear Delay ◽  
Time Amplifier ◽  
Fine Resolution

This paper presents a time-domain CMOS oscillator-based temperature sensor with one-point calibration for test cost reduction. Compared with the former CMOS sensors with linear delay lines, the proposed work composed of a temperature-to-pulse generator with adjustable time gain and a time-to-digital converter (TDC) can achieve lower circuit complexity and smaller area. A temperature-dependent oscillator for temperature sensing was used to generate the period width proportional to absolute temperature (PTAT). With the help of calibration circuit, an adjustable-gain time amplifier was adopted to dynamically adjust the amplified width that was converted by the TDC into the corresponding digital code. After calibration, the fluctuation of the sensor output with process variation can be greatly reduced. The maximum inaccuracy after one-point calibration for six package chips was 1.6 °C within a 0 80 °C temperature range. The proposed sensor fabricated in a 0.35-μm CMOS process occupied a chip area of merely 0.07 mm2, achieved a fine resolution of 0.047 °C/LSB, and consumed a low power of 25 μW@10 samples/s.

scholarly journals Novel Low-Complexity and Low-Power Flip-Flop Design

Electronics ◽  
2020 ◽  
Vol 9 (5) ◽  
pp. 783
Author(s):  
Jin-Fa Lin ◽  
Zheng-Jie Hong ◽  
Chang-Ming Tsai ◽  
Bo-Cheng Wu ◽  
Shao-Wei Yu
Keyword(s):  
Low Power ◽  
Average Power ◽  
Circuit Complexity ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Digital Circuit ◽  
Oxide Semiconductor ◽  
System Level ◽  
Flip Flop ◽  
Chip Area

In this paper, a compact and low-power true single-phase flip-flop (FF) design with fully static operations is presented. The design is developed by using various circuit-reduction schemes and features a hybrid logic style employing both pass transistor logic (PTL) and static complementary metal-oxide semiconductor (CMOS) logic to reduce circuit complexity. These circuit optimization measures pay off in various aspects, including smaller clock-to-Q (CQ) delay, lower average power, lower leakage power, and smaller layout area; and the transistor-count is only 17. Fabricated in TSMC 180 nm CMOS technology, it reduces by over 29% the chip area compared to the conventional transmission gate FF (TGFF). To further show digital circuit/system level advantages, a multi-mode shift register has been realized. Experimental measurement results at 1.8 V/4 MHz show that, compared with the TGFF design, the proposed design saves 64.7% of power consumption while reducing chip area by 26.2%.

A 0.975 μW 10-bit 100 kS/s SAR ADC with an energy-efficient and area-efficient switching scheme

2017 ◽  
Vol 31 (19-21) ◽  
pp. 1740051 ◽  
Author(s):  
Yunfeng Hu ◽  
Chao Xiong ◽  
Bin Li
Keyword(s):  
Power Supply ◽  
Energy Efficient ◽  
Figure Of Merit ◽  
Sampling Rate ◽  
Cmos Technology ◽  
Digital Converter ◽  
Switching Scheme ◽  
Analog To Digital ◽  
Area Reduction ◽  
Area Efficient

A 10-bit successive approximation register (SAR) analog-to-digital converter (ADC) with an energy-efficient and area-efficient switching scheme was presented. By using C-2C dummy capacitor and an extra reference [Formula: see text] for the last capacitor, the proposed switching scheme achieves 97.65% switching energy saving, 87.2% capacitor area reduction and 47.06% switches reduction, compare to conventional switching scheme. The ADC was implemented in a 180 nm CMOS technology 1.8 V power supply, at sampling rate of 100 kS/s, the ADC achieves an SNDR of 57.84 dB and consumes 0.975 [Formula: see text], resulting in a figure-of-merit (FOM) of 15.3 fJ/conversion-step.

Design of Low Voltage Low Power ADC for WSN Node

2013 ◽  
Vol 760-762 ◽  
pp. 561-566
Author(s):  
Si Kui Ren ◽  
Zhi Qun Li
Keyword(s):  
Low Power ◽  
Figure Of Merit ◽  
Dynamic Range ◽  
Low Voltage ◽  
Cmos Technology ◽  
Total Power ◽  
Chip Area ◽  
Analog To Digital ◽  
Spurious Free Dynamic Range ◽  
Free Dynamic

This paper presents a low power low voltage 7bit 16MS/s SAR ADC (successive approximation register analog-to-digital converter) for the application of ZigBee receiver. The proposed 7-bit ADC is designed and simulated in 180nm RF CMOS technology. Post simulation results show that at 1.0-V supply and 16 MS/s, the ADC achieves a SNDR (signal-to-noise-and-distortion ratio) and SFDR (Spurious Free Dynamic Range) are 43.6dB, 57.4dB respectively. The total power dissipation is 228μW, and it occupies a chip area of 0.525 mm2. It results in a figure-of-merit (FOM) of 0.11pJ/step.

scholarly journals Low Power and Area Efficient 4-2 Compressor for Signal Processing Applications

2020 ◽  
Vol 4 (7) ◽  
pp. 8-13
Author(s):  
Mohan Das S ◽  
Ganesh Kumar M ◽  
Shireesha G
Keyword(s):  
Signal Processing ◽  
Low Power ◽  
Energy Efficient ◽  
Performance Metrics ◽  
Supply Voltage ◽  
Average Power ◽  
Cmos Technology ◽  
Fir Filter ◽  
Area Efficient

In this paper, two performance metrics power and delay are estimated for various XOR-XNOR circuits and Multiplexer for designing 4-2 compressor. The main objective is to design an energy efficient compressor for computing applications in FIR filter. The simulations for the designed circuits performed in cadence virtuoso tool with 45 nm CMOS technology at a supply voltage of 0.9 Volts. The proposed 4-2 compressors consist of six blocks out of which two XOR-XNOR blocks and four MUX blocks. The average power, delay and energy consumed by the proposed compressor which is based on 5T XOR-XNOR and GDIMUX design is 85.72 nW, 62.53 pS and 5.36 aJ respectively

60 GHz-Band Low-Noise Amplifier

2017 ◽  
Vol 26 (05) ◽  
pp. 1750075 ◽  
Author(s):  
Najam Muhammad Amin ◽  
Lianfeng Shen ◽  
Zhi-Gong Wang ◽  
Muhammad Ovais Akhter ◽  
Muhammad Tariq Afridi
Keyword(s):  
Transmission Line ◽  
Quality Factor ◽  
Noise Figure ◽  
Cmos Technology ◽  
Low Noise ◽  
Constant Current ◽  
60 Ghz ◽  
Frequency Range ◽  
Constant Current Density ◽  
Chip Area

This paper presents the design of a 60[Formula: see text]GHz-band LNA intended for the 63.72–65.88[Formula: see text]GHz frequency range (channel-4 of the 60[Formula: see text]GHz band). The LNA is designed in a 65-nm CMOS technology and the design methodology is based on a constant-current-density biasing scheme. Prior to designing the LNA, a detailed investigation into the transistor and passives performances at millimeter-wave (MMW) frequencies is carried out. It is shown that biasing the transistors for an optimum noise figure performance does not degrade their power gain significantly. Furthermore, three potential inductive transmission line candidates, based on coplanar waveguide (CPW) and microstrip line (MSL) structures, have been considered to realize the MMW interconnects. Electromagnetic (EM) simulations have been performed to design and compare the performances of these inductive lines. It is shown that the inductive quality factor of a CPW-based inductive transmission line ([Formula: see text] is more than 3.4 times higher than its MSL counterpart @ 65[Formula: see text]GHz. A CPW structure, with an optimized ground-equalizing metal strip density to achieve the highest inductive quality factor, is therefore a preferred choice for the design of MMW interconnects, compared to an MSL. The LNA achieves a measured forward gain of [Formula: see text][Formula: see text]dB with good input and output impedance matching of better than [Formula: see text][Formula: see text]dB in the desired frequency range. Covering a chip area of 1256[Formula: see text][Formula: see text]m[Formula: see text]m including the pads, the LNA dissipates a power of only 16.2[Formula: see text]mW.

scholarly journals An Eye-Safe, SBS-Free Coherent Fiber Laser LIDAR Transmitter with Millijoule Energy and High Average Power

Photonics ◽  
2021 ◽  
Vol 8 (1) ◽  
pp. 15
Author(s):  
Mehmetcan Akbulut ◽  
Leonid Kotov ◽  
Kort Wiersma ◽  
Jie Zong ◽  
Maohe Li ◽  
...  
Keyword(s):  
Fiber Laser ◽  
Repetition Rate ◽  
Peak Power ◽  
Figure Of Merit ◽  
Current System ◽  
Glass Fibers ◽  
Average Power ◽  
High Gain ◽  
Short Length ◽  
High Average Power

We report on an eye-safe, transform-limited, millijoule energy, and high average power fiber laser. The high gain and short length of the NP phosphate-glass fibers enable the SBS-free operation with kW level peak power. The output energy is up to 1.3 mJ, and the average power is up to 23 W at an 18 kHz repetition rate with 600 ns pulses (peak power > 2.1 kW). The PER is ≈16 dB and the M2 of the beam is 1.33 × 1.18. The coherent LIDAR Figure Of Merit (FOM) is 174 mJ*sqrt(Hz), which to our knowledge is the highest reported for a fiber laser. We also report 0.75 mJ energy and >3.7 kW peak power with down to 200 ns pulses and up to 1.21 mJ energy with a 3–5 kHz repetition rate operation of the current system.

scholarly journals LED Rail Signals: Full Hardware Realization of Apparatus with Independent Intensity by Temperature Changes

Electronics ◽  
2021 ◽  
Vol 10 (11) ◽  
pp. 1291
Author(s):  
Giuseppe Schirripa Schirripa Spagnolo ◽  
Fabio Leccese
Keyword(s):  
Temperature Sensor ◽  
Energy Efficient ◽  
Light Emitting Diode ◽  
Junction Temperature ◽  
Light Emitting ◽  
Temperature Changes ◽  
Wide Range ◽  
International Regulations ◽  
Long Lifetime ◽  
Set Up

Nowadays, signal lights are made using light-emitting diode arrays (LEDs). These devices are extremely energy efficient and have a very long lifetime. Unfortunately, especially for yellow/amber LEDs, the intensity of the light is closely related to the junction temperature. This makes it difficult to design signal lights to be used in naval, road, railway, and aeronautical sectors, capable of fully respecting national and international regulations. Furthermore, the limitations prescribed by the standards must be respected in a wide range of temperature variations. In other words, in the signaling apparatuses, a system that varies the light intensity emitted according to the operating temperature is useful/necessary. In this paper, we propose a simple and effective solution. In order to adjust the intensity of the light emitted by the LEDs, we use an LED identical to those used to emit light as a temperature sensor. The proposed system was created and tested in the laboratory. As the same device as the ones to be controlled is used as the temperature sensor, the system is very stable and easy to set up.

Sign in / Sign up

Export Citation Format

Share Document