scholarly journals Custom Memory Design for Logic-in-Memory: Drawbacks and Improvements over Conventional Memories

Electronics ◽  
2021 ◽  
Vol 10 (18) ◽  
pp. 2291
Author(s):  
Fabrizio Ottati ◽  
Giovanna Turvani ◽  
Guido Masera ◽  
Marco Vacca
Keyword(s):  
Energy Consumption ◽  
High Performance ◽  
Data Exchange ◽  
Memory Cell ◽  
Cmos Process ◽  
Memory Array ◽  
Promising Solution ◽  
The Cost ◽  
Array Performance ◽  
Maximum Minimum

The speed of modern digital systems is severely limited by memory latency (the “Memory Wall” problem). Data exchange between Logic and Memory is also responsible for a large part of the system energy consumption. Logic-in-Memory (LiM) represents an attractive solution to this problem. By performing part of the computations directly inside the memory the system speed can be improved while reducing its energy consumption. LiM solutions that offer the major boost in performance are based on the modification of the memory cell. However, what is the cost of such modifications? How do these impact the memory array performance? In this work, this question is addressed by analysing a LiM memory array implementing an algorithm for the maximum/minimum value computation. The memory array is designed at physical level using the FreePDK 45nm CMOS process, with three memory cell variants, and its performance is compared to SRAM and CAM memories. Results highlight that read and write operations performance is worsened but in-memory operations result to be very efficient: a 55.26% reduction in the energy-delay product is measured for the AND operation with respect to the SRAM read one. Therefore, the LiM approach represents a very promising solution for low-density and high-performance memories.

scholarly journals A Bit String Content Aware Chunking Strategy for Reduced CPU Energy on Cloud Storage

2015 ◽  
Vol 2015 ◽  
pp. 1-8 ◽  
Author(s):  
Bin Zhou ◽  
ShuDao Zhang ◽  
Ying Zhang ◽  
JiaHao Tan
Keyword(s):  
Energy Consumption ◽  
Data Center ◽  
System Performance ◽  
Cloud Storage ◽  
High Performance ◽  
Factors Affecting ◽  
Redundant Data ◽  
Energy Factors ◽  
The Cost ◽  
Content Aware

In order to achieve energy saving and reduce the total cost of ownership, green storage has become the first priority for data center. Detecting and deleting the redundant data are the key factors to the reduction of the energy consumption of CPU, while high performance stable chunking strategy provides the groundwork for detecting redundant data. The existing chunking algorithm greatly reduces the system performance when confronted with big data and it wastes a lot of energy. Factors affecting the chunking performance are analyzed and discussed in the paper and a new fingerprint signature calculation is implemented. Furthermore, a Bit String Content Aware Chunking Strategy (BCCS) is put forward. This strategy reduces the cost of signature computation in chunking process to improve the system performance and cuts down the energy consumption of the cloud storage data center. On the basis of relevant test scenarios and test data of this paper, the advantages of the chunking strategy are verified.

scholarly journals Regeneration of Hard Alloy Wastes by Low Energy Consumption and Environmentally Friendly Hydrothermal Technology

2015 ◽  
Vol 16 (1) ◽  
pp. 176-180
Author(s):  
S. F. Korablov
Keyword(s):  
Energy Consumption ◽  
High Performance ◽  
Waste Treatment ◽  
Practical Importance ◽  
Hydrothermal Solution ◽  
Low Energy ◽  
Hard Alloys ◽  
Core Technology ◽  
Low Energy Consumption ◽  
The Cost

Hard alloys are indispensable material for many branches of modern industry. However, even with the base composition (WC-Co) they are quite expensive due to the limited natural resources of cobalt and the complexity of their production from the minerals. Therefore, the collection and recycling of hard alloys waste have not only scientific but practical importance, taking into account that the cost of production of 1 ton of alloy from recovered waste comes to 20% cheaper than in the core technology. Existing methods of hard alloys waste treatment have several disadvantages, the main of which are high power consumption and big load on the environment. As a result of this research a high-performance, low-energy consumption, eco-friendly way for recycling of hard alloys waste has been proposed. According to this technology, in a first step the WC powder, and the solution containing cobalt salts were obtained by autoclaving at 230 °C in a mixture of HCl-H3PO4-HNO3 acids, and followed then metal cobalt  recovery from hydrothermal solution at temperatures of 110 – 160 °C.

scholarly journals Detection of Transient Faults in Nanometer Technologies by using Modular Built-In Current Sensors

2013 ◽  
Vol 8 (2) ◽  
pp. 89-97
Author(s):  
Frank Sill Torres ◽  
Rodrigo Possamai Bastos
Keyword(s):  
Integrated Circuits ◽  
High Performance ◽  
Response Times ◽  
Error Resilience ◽  
Soft Error ◽  
Transient Faults ◽  
Competitive Response ◽  
Promising Solution ◽  
Current Sensors ◽  
The Cost

Soft error resilience is an increasingly important requirement of integrated circuits realized in CMOS nanometer technologies. Among the several approaches, Bulk Built-in Current Sensors (BBICS) offer a promising solution as they are able to detect particle strikes immediately after its occurrence. Based on this idea we demonstrate a novel modular BBICS (mBBICS) that tackles the main problems of these integrated sensors – area, leakage, and robustness. Simulations based on a predictive nanometer technology indicate competitive response times for high performance applications at the cost of 25 % area overhead and very low power penalty. Thereby, all simulated particle strikes that lead to transient faults could be detected. Additionally, reliability analysis proved the robustness of the proposed mBBICS against wide variations of temperature and process parameters.

Profile-Guided Optimization of System Energy Consumption for High-Performance Operational Applications

2014 ◽  
Vol 24 (8) ◽  
pp. 1761-1774
Author(s):  
Hui-Zhan YI ◽  
Zhao-Cheng LUO
Keyword(s):  
Energy Consumption ◽  
High Performance ◽  
System Energy

scholarly journals A Novel Fast-Locking ADPLL Based on Bisection Method

Electronics ◽  
2021 ◽  
Vol 10 (12) ◽  
pp. 1382
Author(s):  
Xiaoying Deng ◽  
Huazhang Li ◽  
Mingcheng Zhu
Keyword(s):  
High Performance ◽  
Tuning Range ◽  
Frequency Control ◽  
Control Word ◽  
Cmos Process ◽  
Bisection Method ◽  
Reference Frequency ◽  
Wide Tuning Range ◽  
Cascade Structure ◽  
And Control

Based on the idea of bisection method, a new structure of All-Digital Phased-Locked Loop (ADPLL) with fast-locking is proposed. The structure and locking method are different from the traditional ADPLLs. The Control Circuit consists of frequency compare module, mode-adjust module and control module, which is responsible for adjusting the frequency control word of digital-controlled-oscillator (DCO) by Bisection method according to the result of the frequency compare between reference clock and restructure clock. With a high frequency cascade structure, the DCO achieves wide tuning range and high resolution. The proposed ADPLL was designed in SMIC 180 nm CMOS process. The measured results show a lock range of 640-to-1920 MHz with a 40 MHz reference frequency. The ADPLL core occupies 0.04 mm2, and the power consumption is 29.48 mW, with a 1.8 V supply. The longest locking time is 23 reference cycles, 575 ns, at 1.92 GHz. When the ADPLL operates at 1.28 GHz–1.6 GHz, the locking time is the shortest, only 9 reference cycles, 225 ns. Compared with the recent high-performance ADPLLs, our design shows advantages of small area, short locking time, and wide tuning range.

scholarly journals Energy Saving Quantitative Analysis of Passive, Active, and Renewable Technologies in Different Climate Zones

2021 ◽  
Vol 11 (15) ◽  
pp. 7115
Author(s):  
Chul-Ho Kim ◽  
Min-Kyeong Park ◽  
Won-Hee Kang
Keyword(s):  
Renewable Energy ◽  
Energy Consumption ◽  
Energy Saving ◽  
High Performance ◽  
Energy Systems ◽  
Outdoor Air ◽  
Climate Zones ◽  
Renewable Energy Systems ◽  
Active Systems ◽  
High Performance Buildings

The purpose of this study was to provide a guideline for the selection of technologies suitable for ASHRAE international climate zones when designing high-performance buildings. In this study, high-performance technologies were grouped as passive, active, and renewable energy systems. Energy saving technologies comprising 15 cases were categorized into passive, active, and renewable energy systems. EnergyPlus v9.5.0 was used to analyze the contribution of each technology in reducing the primary energy consumption. The energy consumption of each system was analyzed in different climates (Incheon, New Delhi, Minneapolis, Berlin), and the detailed contributions to saving energy were evaluated. Even when the same technology is applied, the energy saving rate differs according to the climatic characteristics. Shading systems are passive systems that are more effective in hot regions. In addition, the variable air volume (VAV) system, combined VAV–energy recovery ventilation (ERV), and combined VAV–underfloor air distribution (UFAD) are active systems that can convert hot and humid outdoor temperatures to create comfortable indoor environments. In cold and cool regions, passive systems that prevent heat loss, such as high-R insulation walls and windows, are effective. Active systems that utilize outdoor air or ventilation include the combined VAV-economizer, the active chilled beam with dedicated outdoor air system (DOAS), and the combined VAV-ERV. For renewable energy systems, the ground source heat pump (GSHP) is more effective. Selecting energy saving technologies that are suitable for the surrounding environment, and selecting design strategies that are appropriate for a given climate, are very important for the design of high-performance buildings globally.

scholarly journals Porous Carbon Architecture Assembled by Cross-Linked Carbon Leaves with Implanted Atomic Cobalt for High-Performance Li–S Batteries

2021 ◽  
Vol 13 (1) ◽  
Author(s):  
Ruirui Wang ◽  
Renbing Wu ◽  
Chaofan Ding ◽  
Ziliang Chen ◽  
Hongbin Xu ◽  
...  
Keyword(s):  
Active Sites ◽  
High Performance ◽  
Specific Capacity ◽  
Three Dimension ◽  
Zeolitic Imidazolate Framework ◽  
Shuttle Effect ◽  
Promising Solution ◽  
Fading Rate ◽  
Kinetics Of ◽  
Sulfur Cathodes

AbstractThe practical application of lithium–sulfur batteries is severely hampered by the poor conductivity, polysulfide shuttle effect and sluggish reaction kinetics of sulfur cathodes. Herein, a hierarchically porous three-dimension (3D) carbon architecture assembled by cross-linked carbon leaves with implanted atomic Co–N4 has been delicately developed as an advanced sulfur host through a SiO2-mediated zeolitic imidazolate framework-L (ZIF-L) strategy. The unique 3D architectures not only provide a highly conductive network for fast electron transfer and buffer the volume change upon lithiation–delithiation process but also endow rich interface with full exposure of Co–N4 active sites to boost the lithium polysulfides adsorption and conversion. Owing to the accelerated kinetics and suppressed shuttle effect, the as-prepared sulfur cathode exhibits a superior electrochemical performance with a high reversible specific capacity of 695 mAh g−1 at 5 C and a low capacity fading rate of 0.053% per cycle over 500 cycles at 1 C. This work may provide a promising solution for the design of an advanced sulfur-based cathode toward high-performance Li–S batteries.

LOW-POWER, PARALLEL INTERFACE WITH CONTINUOUS-TIME ADAPTIVE PASSIVE EQUALIZER AND CROSSTALK CANCELLATION

2005 ◽  
Vol 15 (02) ◽  
pp. 459-476
Author(s):  
C. PATRICK YUE ◽  
JAEJIN PARK ◽  
RUIFENG SUN ◽  
L. RICK CARLEY ◽  
FRANK O'MAHONY
Keyword(s):  
Low Power ◽  
Electromagnetic Interference ◽  
Continuous Time ◽  
High Speed ◽  
High Performance ◽  
Process Variations ◽  
Cmos Process ◽  
Power Circuit ◽  
Crosstalk Cancellation ◽  
Circuit Components

This paper presents the low-power circuit techniques suitable for high-speed digital parallel interfaces each operating at over 10 Gbps. One potential application for such high-performance I/Os is the interface between the channel IC and the magnetic read head in future compact hard disk systems. First, a crosstalk cancellation technique using a novel data encoding scheme is introduced to suppress electromagnetic interference (EMI) generated by the adjacent parallel I/Os . This technique is implemented utilizing a novel 8-4-PAM signaling with a data look-ahead algorithm. The key circuit components in the high-speed interface transceiver including the receive sampler, the phase interpolator, and the transmitter output driver are described in detail. Designed in a 0.13-μm digital CMOS process, the transceiver consumes 310 mW per 10-Gps channel from a I-V supply based on simulation results. Next, a 20-Gbps continuous-time adaptive passive equalizer utilizing on-chip lumped RLC components is described. Passive equalizers offer the advantages of higher bandwidth and lower power consumption compared with conventional designs using active filter. A low-power, continuous-time servo loop is designed to automatically adjust the equalizer frequency response for the optimal gain compensation. The equalizer not only adapts to different channel characteristics, but also accommodates temperature and process variations. Implemented in a 0.25-μm, 1P6M BiCMOS process, the equalizer can compensate up to 20 dB of loss at 10 GHz while only consumes 32 mW from a 2.5-V supply.

RECENT DEVELOPMENTS ON 3D INTEGRATION OF METALLIC SET ONTO CMOS PROCESS FOR MEMORY APPLICATION

2012 ◽  
Vol 11 (04) ◽  
pp. 1240024 ◽  
Author(s):  
N. JOUVET ◽  
M. A. BOUNOUAR ◽  
S. ECOFFEY ◽  
C. NAUENHEIM ◽  
A. BEAUMONT ◽  
...  
Keyword(s):  
Room Temperature ◽  
Memory Cell ◽  
Atomic Layer ◽  
Cmos Process ◽  
3D Integration ◽  
Simulation Tools ◽  
Layer Deposition ◽  
Recent Developments ◽  
Sram Memory ◽  
Electrical Characterizations

This work presents a nanodamascene process for a CMOS back-end-of-line fabrication of metallic single electron transistor(SET), together with the use of simulation tools for the development of a SET SRAM memory cell. We show room temperature electrical characterizations of SETs fabricated on CMOS with relaxed dimensions, and simulations of a SET SRAM memory cell. Using their physical characteristics achievable through the use of atomic layer deposition, it will be demonstrated that it has the potential to operate at temperature up to 398 K, and that power consumption is less than that of equivalent circuit in advanced CMOS technologies. In order to take advantage of both low power SETs and high CMOS drive efficiency, a hybrid 3D SET CMOS circuit is proposed.

Sign in / Sign up

Export Citation Format

Share Document